@@ -23,13 +23,14 @@ optional external memory-mapped interface.
23
23
24
24
Version 1 of the Activity Monitors architecture implements a counter group
25
25
of four fixed and architecturally defined 64-bit event counters.
26
- - CPU cycle counter: increments at the frequency of the CPU.
27
- - Constant counter: increments at the fixed frequency of the system
28
- clock.
29
- - Instructions retired: increments with every architecturally executed
30
- instruction.
31
- - Memory stall cycles: counts instruction dispatch stall cycles caused by
32
- misses in the last level cache within the clock domain.
26
+
27
+ - CPU cycle counter: increments at the frequency of the CPU.
28
+ - Constant counter: increments at the fixed frequency of the system
29
+ clock.
30
+ - Instructions retired: increments with every architecturally executed
31
+ instruction.
32
+ - Memory stall cycles: counts instruction dispatch stall cycles caused by
33
+ misses in the last level cache within the clock domain.
33
34
34
35
When in WFI or WFE these counters do not increment.
35
36
@@ -57,11 +58,12 @@ counters, only the presence of the extension.
57
58
58
59
Firmware (code running at higher exception levels, e.g. arm-tf) support is
59
60
needed to:
60
- - Enable access for lower exception levels (EL2 and EL1) to the AMU
61
- registers.
62
- - Enable the counters. If not enabled these will read as 0.
63
- - Save/restore the counters before/after the CPU is being put/brought up
64
- from the 'off' power state.
61
+
62
+ - Enable access for lower exception levels (EL2 and EL1) to the AMU
63
+ registers.
64
+ - Enable the counters. If not enabled these will read as 0.
65
+ - Save/restore the counters before/after the CPU is being put/brought up
66
+ from the 'off' power state.
65
67
66
68
When using kernels that have this feature enabled but boot with broken
67
69
firmware the user may experience panics or lockups when accessing the
@@ -78,10 +80,11 @@ are not trapped in EL2/EL3.
78
80
79
81
The fixed counters of AMUv1 are accessible though the following system
80
82
register definitions:
81
- - SYS_AMEVCNTR0_CORE_EL0
82
- - SYS_AMEVCNTR0_CONST_EL0
83
- - SYS_AMEVCNTR0_INST_RET_EL0
84
- - SYS_AMEVCNTR0_MEM_STALL_EL0
83
+
84
+ - SYS_AMEVCNTR0_CORE_EL0
85
+ - SYS_AMEVCNTR0_CONST_EL0
86
+ - SYS_AMEVCNTR0_INST_RET_EL0
87
+ - SYS_AMEVCNTR0_MEM_STALL_EL0
85
88
86
89
Auxiliary platform specific counters can be accessed using
87
90
SYS_AMEVCNTR1_EL0(n), where n is a value between 0 and 15.
@@ -93,9 +96,10 @@ Userspace access
93
96
----------------
94
97
95
98
Currently, access from userspace to the AMU registers is disabled due to:
96
- - Security reasons: they might expose information about code executed in
97
- secure mode.
98
- - Purpose: AMU counters are intended for system management use.
99
+
100
+ - Security reasons: they might expose information about code executed in
101
+ secure mode.
102
+ - Purpose: AMU counters are intended for system management use.
99
103
100
104
Also, the presence of the feature is not visible to userspace.
101
105
@@ -105,8 +109,9 @@ Virtualization
105
109
106
110
Currently, access from userspace (EL0) and kernelspace (EL1) on the KVM
107
111
guest side is disabled due to:
108
- - Security reasons: they might expose information about code executed
109
- by other guests or the host.
112
+
113
+ - Security reasons: they might expose information about code executed
114
+ by other guests or the host.
110
115
111
116
Any attempt to access the AMU registers will result in an UNDEFINED
112
117
exception being injected into the guest.
0 commit comments