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Merge tag 'perf-tools-for-v5.19-2022-06-04' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux
Pull more perf tools updates from Arnaldo Carvalho de Melo: - Synthesize task events for pre-existing threads when using 'perf lock --threads', as we need to show task names. - Fix unwinding with ld.lld (>= version 10.0) linked objects, where .eh_frame_hdr and .text are in different PT_LOAD program headers, which makes perf record --call-graph dwarf fail with such obkects. - Check if 'perf record' hangs in the ARM SPE (Statistical Profiling Extensions) 'perf test' entry when recording a workload with forks. - Trace physical address for Arm SPE events, needed for 'perf c2c' to locate the memory node for samples. - Fix sorting in percent_rmt_hitm_cmp() in 'perf c2c'. - Further support for Intel hybrid systems in the evlist and 'perf record' code. - Update IBM s/390 vendor event JSON tables. - Add metrics (JSON) for Intel Sapphirerapids. - Update metrics for Intel Alderlake. - Correct typo of sysf 'event_source' directory in the documentation. * tag 'perf-tools-for-v5.19-2022-06-04' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux: perf vendor events intel: Update metrics for Alderlake perf vendor events intel: Add metrics for Sapphirerapids perf c2c: Fix sorting in percent_rmt_hitm_cmp() perf mem: Trace physical address for Arm SPE events perf list: Update event description for IBM zEC12/zBC12 to latest level perf list: Update event description for IBM z196/z114 to latest level perf list: Update event description for IBM z15 to latest level perf list: Update event description for IBM z14 to latest level perf list: Update event description for IBM z13 to latest level perf list: Update event description for IBM z10 to latest level perf list: Add IBM z16 event description for s390 perf record: Support sample-read topdown metric group for hybrid platforms perf lock: Change to synthesize task events perf unwind: Fix segbase for ld.lld linked objects perf test arm-spe: Check if perf-record hangs when recording workload with forks perf docs: Correct typo of event_sources perf evlist: Extend arch_evsel__must_be_in_group to support hybrid systems
2 parents 032dcf0 + 1bcca2b commit 45b2e5a

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‎tools/perf/Documentation/perf-record.txt

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@@ -33,7 +33,7 @@ OPTIONS
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- a raw PMU event in the form of rN where N is a hexadecimal value
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that represents the raw register encoding with the layout of the
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event control registers as described by entries in
36-
/sys/bus/event_sources/devices/cpu/format/*.
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/sys/bus/event_source/devices/cpu/format/*.
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- a symbolic or raw PMU event followed by an optional colon
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and a list of event modifiers, e.g., cpu-cycles:p. See the

‎tools/perf/Documentation/perf-stat.txt

Lines changed: 1 addition & 1 deletion
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@@ -39,7 +39,7 @@ report::
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- a raw PMU event in the form of rN where N is a hexadecimal value
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that represents the raw register encoding with the layout of the
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event control registers as described by entries in
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/sys/bus/event_sources/devices/cpu/format/*.
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/sys/bus/event_source/devices/cpu/format/*.
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- a symbolic or raw PMU event followed by an optional colon
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and a list of event modifiers, e.g., cpu-cycles:p. See the

‎tools/perf/Documentation/perf-top.txt

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@@ -41,7 +41,7 @@ Default is to monitor all CPUS.
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(use 'perf list' to list all events) or a raw PMU event in the form
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of rN where N is a hexadecimal value that represents the raw register
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encoding with the layout of the event control registers as described
44-
by entries in /sys/bus/event_sources/devices/cpu/format/*.
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by entries in /sys/bus/event_source/devices/cpu/format/*.
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-E <entries>::
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--entries=<entries>::

‎tools/perf/arch/arm64/util/mem-events.c

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@@ -5,9 +5,9 @@
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#define E(t, n, s) { .tag = t, .name = n, .sysfs_name = s }
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static struct perf_mem_event perf_mem_events[PERF_MEM_EVENTS__MAX] = {
8-
E("spe-load", "arm_spe_0/ts_enable=1,load_filter=1,store_filter=0,min_latency=%u/", "arm_spe_0"),
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E("spe-store", "arm_spe_0/ts_enable=1,load_filter=0,store_filter=1/", "arm_spe_0"),
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E("spe-ldst", "arm_spe_0/ts_enable=1,load_filter=1,store_filter=1,min_latency=%u/", "arm_spe_0"),
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E("spe-load", "arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,store_filter=0,min_latency=%u/", "arm_spe_0"),
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E("spe-store", "arm_spe_0/ts_enable=1,pa_enable=1,load_filter=0,store_filter=1/", "arm_spe_0"),
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E("spe-ldst", "arm_spe_0/ts_enable=1,pa_enable=1,load_filter=1,store_filter=1,min_latency=%u/", "arm_spe_0"),
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};
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static char mem_ev_name[100];

‎tools/perf/arch/x86/util/evsel.c

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@@ -5,6 +5,7 @@
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#include "util/env.h"
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#include "util/pmu.h"
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#include "linux/string.h"
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#include "evsel.h"
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void arch_evsel__set_sample_weight(struct evsel *evsel)
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{
@@ -32,7 +33,7 @@ void arch_evsel__fixup_new_cycles(struct perf_event_attr *attr)
3233
}
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/* Check whether the evsel's PMU supports the perf metrics */
35-
static bool evsel__sys_has_perf_metrics(const struct evsel *evsel)
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bool evsel__sys_has_perf_metrics(const struct evsel *evsel)
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{
3738
const char *pmu_name = evsel->pmu_name ? evsel->pmu_name : "cpu";
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@@ -57,6 +58,6 @@ bool arch_evsel__must_be_in_group(const struct evsel *evsel)
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return false;
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5960
return evsel->name &&
60-
(!strcasecmp(evsel->name, "slots") ||
61+
(strcasestr(evsel->name, "slots") ||
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strcasestr(evsel->name, "topdown"));
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}

‎tools/perf/arch/x86/util/evsel.h

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@@ -0,0 +1,7 @@
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/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _EVSEL_H
3+
#define _EVSEL_H 1
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5+
bool evsel__sys_has_perf_metrics(const struct evsel *evsel);
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#endif

‎tools/perf/arch/x86/util/topdown.c

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@@ -4,6 +4,7 @@
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#include "util/pmu.h"
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#include "util/topdown.h"
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#include "topdown.h"
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#include "evsel.h"
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/* Check whether there is a PMU which supports the perf metrics. */
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bool topdown_sys_has_perf_metrics(void)
@@ -55,33 +56,19 @@ void arch_topdown_group_warn(void)
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#define TOPDOWN_SLOTS 0x0400
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58-
static bool is_topdown_slots_event(struct evsel *counter)
59-
{
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if (!counter->pmu_name)
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return false;
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if (strcmp(counter->pmu_name, "cpu"))
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return false;
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if (counter->core.attr.config == TOPDOWN_SLOTS)
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return true;
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return false;
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}
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/*
7360
* Check whether a topdown group supports sample-read.
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*
75-
* Only Topdown metic supports sample-read. The slots
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* Only Topdown metric supports sample-read. The slots
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* event must be the leader of the topdown group.
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*/
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bool arch_topdown_sample_read(struct evsel *leader)
8067
{
81-
if (!pmu_have_event("cpu", "slots"))
68+
if (!evsel__sys_has_perf_metrics(leader))
8269
return false;
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84-
if (is_topdown_slots_event(leader))
71+
if (leader->core.attr.config == TOPDOWN_SLOTS)
8572
return true;
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return false;

‎tools/perf/builtin-c2c.c

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@@ -928,8 +928,8 @@ percent_rmt_hitm_cmp(struct perf_hpp_fmt *fmt __maybe_unused,
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double per_left;
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double per_right;
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931-
per_left = PERCENT(left, lcl_hitm);
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per_right = PERCENT(right, lcl_hitm);
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per_left = PERCENT(left, rmt_hitm);
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per_right = PERCENT(right, rmt_hitm);
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return per_left - per_right;
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}

‎tools/perf/builtin-lock.c

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@@ -1083,7 +1083,7 @@ static int __cmd_report(bool display_info)
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static int __cmd_record(int argc, const char **argv)
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{
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const char *record_args[] = {
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"record", "-R", "-m", "1024", "-c", "1", "--synth", "no",
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"record", "-R", "-m", "1024", "-c", "1", "--synth", "task",
10871087
};
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unsigned int rec_argc, i, j, ret;
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const char **rec_argv;

‎tools/perf/pmu-events/arch/s390/cf_z10/basic.json

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@@ -3,84 +3,84 @@
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"Unit": "CPU-M-CF",
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"EventCode": "0",
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"EventName": "CPU_CYCLES",
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"BriefDescription": "CPU Cycles",
7-
"PublicDescription": "Cycle Count"
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"BriefDescription": "Cycle Count",
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"PublicDescription": "This counter counts the total number of CPU cycles, excluding the number of cycles while the CPU is in the wait state."
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},
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{
1010
"Unit": "CPU-M-CF",
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"EventCode": "1",
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"EventName": "INSTRUCTIONS",
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"BriefDescription": "Instructions",
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"PublicDescription": "Instruction Count"
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"BriefDescription": "Instruction Count",
14+
"PublicDescription": "This counter counts the total number of instructions executed by the CPU."
1515
},
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{
1717
"Unit": "CPU-M-CF",
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"EventCode": "2",
1919
"EventName": "L1I_DIR_WRITES",
20-
"BriefDescription": "L1I Directory Writes",
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"PublicDescription": "Level-1 I-Cache Directory Write Count"
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"BriefDescription": "Level-1 I-Cache Directory Write Count",
21+
"PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes."
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},
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{
2424
"Unit": "CPU-M-CF",
2525
"EventCode": "3",
2626
"EventName": "L1I_PENALTY_CYCLES",
27-
"BriefDescription": "L1I Penalty Cycles",
28-
"PublicDescription": "Level-1 I-Cache Penalty Cycle Count"
27+
"BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
28+
"PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 instruction cache or unified cache."
2929
},
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{
3131
"Unit": "CPU-M-CF",
3232
"EventCode": "4",
3333
"EventName": "L1D_DIR_WRITES",
34-
"BriefDescription": "L1D Directory Writes",
35-
"PublicDescription": "Level-1 D-Cache Directory Write Count"
34+
"BriefDescription": "Level-1 D-Cache Directory Write Count",
35+
"PublicDescription": "This counter counts the total number of level-1 data-cache directory writes."
3636
},
3737
{
3838
"Unit": "CPU-M-CF",
3939
"EventCode": "5",
4040
"EventName": "L1D_PENALTY_CYCLES",
41-
"BriefDescription": "L1D Penalty Cycles",
42-
"PublicDescription": "Level-1 D-Cache Penalty Cycle Count"
41+
"BriefDescription": "Level-1 D-Cache Penalty Cycle Count",
42+
"PublicDescription": "This counter counts the total number of cache penalty cycles for level-1 data cache."
4343
},
4444
{
4545
"Unit": "CPU-M-CF",
4646
"EventCode": "32",
4747
"EventName": "PROBLEM_STATE_CPU_CYCLES",
48-
"BriefDescription": "Problem-State CPU Cycles",
49-
"PublicDescription": "Problem-State Cycle Count"
48+
"BriefDescription": "Problem-State Cycle Count",
49+
"PublicDescription": "This counter counts the total number of CPU cycles when the CPU is in the problem state, excluding the number of cycles while the CPU is in the wait state."
5050
},
5151
{
5252
"Unit": "CPU-M-CF",
5353
"EventCode": "33",
5454
"EventName": "PROBLEM_STATE_INSTRUCTIONS",
55-
"BriefDescription": "Problem-State Instructions",
56-
"PublicDescription": "Problem-State Instruction Count"
55+
"BriefDescription": "Problem-State Instruction Count",
56+
"PublicDescription": "This counter counts the total number of instructions executed by the CPU while in the problem state."
5757
},
5858
{
5959
"Unit": "CPU-M-CF",
6060
"EventCode": "34",
6161
"EventName": "PROBLEM_STATE_L1I_DIR_WRITES",
62-
"BriefDescription": "Problem-State L1I Directory Writes",
63-
"PublicDescription": "Problem-State Level-1 I-Cache Directory Write Count"
62+
"BriefDescription": "Problem-State Level-1 I-Cache Directory Write Count",
63+
"PublicDescription": "This counter counts the total number of level-1 instruction-cache or unified-cache directory writes while the CPU is in the problem state."
6464
},
6565
{
6666
"Unit": "CPU-M-CF",
6767
"EventCode": "35",
6868
"EventName": "PROBLEM_STATE_L1I_PENALTY_CYCLES",
69-
"BriefDescription": "Problem-State L1I Penalty Cycles",
70-
"PublicDescription": "Problem-State Level-1 I-Cache Penalty Cycle Count"
69+
"BriefDescription": "Level-1 I-Cache Penalty Cycle Count",
70+
"PublicDescription": "This counter counts the total number of penalty cycles for level-1 instruction cache or unified cache while the CPU is in the problem state."
7171
},
7272
{
7373
"Unit": "CPU-M-CF",
7474
"EventCode": "36",
7575
"EventName": "PROBLEM_STATE_L1D_DIR_WRITES",
76-
"BriefDescription": "Problem-State L1D Directory Writes",
77-
"PublicDescription": "Problem-State Level-1 D-Cache Directory Write Count"
76+
"BriefDescription": "Problem-State Level-1 D-Cache Directory Write Count",
77+
"PublicDescription": "This counter counts the total number of level-1 data-cache directory writes while the CPU is in the problem state."
7878
},
7979
{
8080
"Unit": "CPU-M-CF",
8181
"EventCode": "37",
8282
"EventName": "PROBLEM_STATE_L1D_PENALTY_CYCLES",
83-
"BriefDescription": "Problem-State L1D Penalty Cycles",
84-
"PublicDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count"
83+
"BriefDescription": "Problem-State Level-1 D-Cache Penalty Cycle Count",
84+
"PublicDescription": "This counter counts the total number of penalty cycles for level-1 data cache while the CPU is in the problem state."
8585
}
8686
]

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