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#define NUM_COUNTERS 11
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#define CYCLES_COUNTER 0
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+ #define CONFIG_EVENT_MASK GENMASK(7, 0)
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+ #define CONFIG_COUNTER_MASK GENMASK(15, 8)
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+
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#define to_ddr_pmu (p ) container_of(p, struct ddr_pmu, pmu)
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#define DDR_PERF_DEV_NAME "imx9_ddr"
@@ -339,8 +342,10 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config,
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int counter , bool enable )
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{
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u32 ctrl_a ;
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+ int event ;
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ctrl_a = readl_relaxed (pmu -> base + PMLCA (counter ));
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+ event = FIELD_GET (CONFIG_EVENT_MASK , config );
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if (enable ) {
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ctrl_a |= PMLCA_FC ;
@@ -352,7 +357,7 @@ static void ddr_perf_counter_local_config(struct ddr_pmu *pmu, int config,
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ctrl_a &= ~PMLCA_FC ;
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ctrl_a |= PMLCA_CE ;
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ctrl_a &= ~FIELD_PREP (PMLCA_EVENT , 0x7F );
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- ctrl_a |= FIELD_PREP (PMLCA_EVENT , ( config & 0x000000FF ) );
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+ ctrl_a |= FIELD_PREP (PMLCA_EVENT , event );
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writel (ctrl_a , pmu -> base + PMLCA (counter ));
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} else {
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/* Freeze counter. */
@@ -366,8 +371,8 @@ static void ddr_perf_monitor_config(struct ddr_pmu *pmu, int cfg, int cfg1, int
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u32 pmcfg1 , pmcfg2 ;
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int event , counter ;
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- event = cfg & 0x000000FF ;
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- counter = ( cfg & 0x0000FF00 ) >> 8 ;
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+ event = FIELD_GET ( CONFIG_EVENT_MASK , cfg ) ;
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+ counter = FIELD_GET ( CONFIG_COUNTER_MASK , cfg ) ;
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pmcfg1 = readl_relaxed (pmu -> base + PMCFG1 );
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@@ -469,7 +474,7 @@ static int ddr_perf_event_add(struct perf_event *event, int flags)
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int cfg2 = event -> attr .config2 ;
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int counter ;
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- counter = ( cfg & 0x0000FF00 ) >> 8 ;
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+ counter = FIELD_GET ( CONFIG_COUNTER_MASK , cfg ) ;
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pmu -> events [counter ] = event ;
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pmu -> active_events ++ ;
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