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airliedairlied
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Merge tag 'amd-drm-fixes-5.9-2020-08-12' of git://people.freedesktop.org/~agd5f/linux into drm-fixes
amd-drm-fixes-5.9-2020-08-12: amdgpu: - Fix allocation size - SR-IOV fixes - Vega20 SMU feature state caching fix - Fix custom pptable handling - Arcturus golden settings update - Several display fixes Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents f2ea257 + f41ed88 commit 485d41b

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12 files changed

+114
-45
lines changed

12 files changed

+114
-45
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -462,7 +462,7 @@ int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,
462462
unsigned int pages;
463463
int i, r;
464464

465-
*sgt = kmalloc(sizeof(*sg), GFP_KERNEL);
465+
*sgt = kmalloc(sizeof(**sgt), GFP_KERNEL);
466466
if (!*sgt)
467467
return -ENOMEM;
468468

‎drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -691,6 +691,7 @@ static const struct soc15_reg_golden golden_settings_gc_9_4_1_arct[] =
691691
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_5_ARCT, 0x3ff, 0x135),
692692
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xffffffff, 0x011A0000),
693693
SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_FIFO_SIZES, 0xffffffff, 0x00000f00),
694+
SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_UTCL1_CNTL1, 0x30000000, 0x30000000)
694695
};
695696

696697
static const struct soc15_reg_rlcg rlcg_access_gc_9_0[] = {

‎drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.c

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -135,6 +135,12 @@ static void gfxhub_v2_1_init_cache_regs(struct amdgpu_device *adev)
135135
{
136136
uint32_t tmp;
137137

138+
/* These registers are not accessible to VF-SRIOV.
139+
* The PF will program them instead.
140+
*/
141+
if (amdgpu_sriov_vf(adev))
142+
return;
143+
138144
/* Setup L2 cache */
139145
tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_CNTL);
140146
tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1);
@@ -190,6 +196,12 @@ static void gfxhub_v2_1_enable_system_domain(struct amdgpu_device *adev)
190196

191197
static void gfxhub_v2_1_disable_identity_aperture(struct amdgpu_device *adev)
192198
{
199+
/* These registers are not accessible to VF-SRIOV.
200+
* The PF will program them instead.
201+
*/
202+
if (amdgpu_sriov_vf(adev))
203+
return;
204+
193205
WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
194206
0xFFFFFFFF);
195207
WREG32_SOC15(GC, 0, mmGCVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
@@ -326,6 +338,13 @@ void gfxhub_v2_1_set_fault_enable_default(struct amdgpu_device *adev,
326338
bool value)
327339
{
328340
u32 tmp;
341+
342+
/* These registers are not accessible to VF-SRIOV.
343+
* The PF will program them instead.
344+
*/
345+
if (amdgpu_sriov_vf(adev))
346+
return;
347+
329348
tmp = RREG32_SOC15(GC, 0, mmGCVM_L2_PROTECTION_FAULT_CNTL);
330349
tmp = REG_SET_FIELD(tmp, GCVM_L2_PROTECTION_FAULT_CNTL,
331350
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);

‎drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.c

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -134,6 +134,12 @@ static void mmhub_v2_0_init_cache_regs(struct amdgpu_device *adev)
134134
{
135135
uint32_t tmp;
136136

137+
/* These registers are not accessible to VF-SRIOV.
138+
* The PF will program them instead.
139+
*/
140+
if (amdgpu_sriov_vf(adev))
141+
return;
142+
137143
/* Setup L2 cache */
138144
tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_CNTL);
139145
tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1);
@@ -189,6 +195,12 @@ static void mmhub_v2_0_enable_system_domain(struct amdgpu_device *adev)
189195

190196
static void mmhub_v2_0_disable_identity_aperture(struct amdgpu_device *adev)
191197
{
198+
/* These registers are not accessible to VF-SRIOV.
199+
* The PF will program them instead.
200+
*/
201+
if (amdgpu_sriov_vf(adev))
202+
return;
203+
192204
WREG32_SOC15(MMHUB, 0,
193205
mmMMVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
194206
0xFFFFFFFF);
@@ -318,6 +330,13 @@ void mmhub_v2_0_gart_disable(struct amdgpu_device *adev)
318330
void mmhub_v2_0_set_fault_enable_default(struct amdgpu_device *adev, bool value)
319331
{
320332
u32 tmp;
333+
334+
/* These registers are not accessible to VF-SRIOV.
335+
* The PF will program them instead.
336+
*/
337+
if (amdgpu_sriov_vf(adev))
338+
return;
339+
321340
tmp = RREG32_SOC15(MMHUB, 0, mmMMVM_L2_PROTECTION_FAULT_CNTL);
322341
tmp = REG_SET_FIELD(tmp, MMVM_L2_PROTECTION_FAULT_CNTL,
323342
RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2196,6 +2196,7 @@ void amdgpu_dm_update_connector_after_detect(
21962196

21972197
drm_connector_update_edid_property(connector,
21982198
aconnector->edid);
2199+
drm_add_edid_modes(connector, aconnector->edid);
21992200

22002201
if (aconnector->dc_link->aux_mode)
22012202
drm_dp_cec_set_edid(&aconnector->dm_dp_aux.aux,

‎drivers/gpu/drm/amd/display/dc/core/dc_link.c

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3286,12 +3286,11 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
32863286
core_link_set_avmute(pipe_ctx, true);
32873287
}
32883288

3289+
dc->hwss.blank_stream(pipe_ctx);
32893290
#if defined(CONFIG_DRM_AMD_DC_HDCP)
32903291
update_psp_stream_config(pipe_ctx, true);
32913292
#endif
32923293

3293-
dc->hwss.blank_stream(pipe_ctx);
3294-
32953294
if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
32963295
deallocate_mst_payload(pipe_ctx);
32973296

‎drivers/gpu/drm/amd/display/dc/dce/dce_panel_cntl.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -49,7 +49,7 @@
4949
#define DCN_PANEL_CNTL_REG_LIST()\
5050
DCN_PANEL_CNTL_SR(PWRSEQ_CNTL, LVTMA), \
5151
DCN_PANEL_CNTL_SR(PWRSEQ_STATE, LVTMA), \
52-
DCE_PANEL_CNTL_SR(PWRSEQ_REF_DIV, LVTMA), \
52+
DCN_PANEL_CNTL_SR(PWRSEQ_REF_DIV, LVTMA), \
5353
SR(BL_PWM_CNTL), \
5454
SR(BL_PWM_CNTL2), \
5555
SR(BL_PWM_PERIOD_CNTL), \

‎drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -121,35 +121,35 @@ void enc1_update_generic_info_packet(
121121
switch (packet_index) {
122122
case 0:
123123
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
124-
AFMT_GENERIC0_FRAME_UPDATE, 1);
124+
AFMT_GENERIC0_IMMEDIATE_UPDATE, 1);
125125
break;
126126
case 1:
127127
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
128-
AFMT_GENERIC1_FRAME_UPDATE, 1);
128+
AFMT_GENERIC1_IMMEDIATE_UPDATE, 1);
129129
break;
130130
case 2:
131131
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
132-
AFMT_GENERIC2_FRAME_UPDATE, 1);
132+
AFMT_GENERIC2_IMMEDIATE_UPDATE, 1);
133133
break;
134134
case 3:
135135
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
136-
AFMT_GENERIC3_FRAME_UPDATE, 1);
136+
AFMT_GENERIC3_IMMEDIATE_UPDATE, 1);
137137
break;
138138
case 4:
139139
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
140-
AFMT_GENERIC4_FRAME_UPDATE, 1);
140+
AFMT_GENERIC4_IMMEDIATE_UPDATE, 1);
141141
break;
142142
case 5:
143143
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
144-
AFMT_GENERIC5_FRAME_UPDATE, 1);
144+
AFMT_GENERIC5_IMMEDIATE_UPDATE, 1);
145145
break;
146146
case 6:
147147
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
148-
AFMT_GENERIC6_FRAME_UPDATE, 1);
148+
AFMT_GENERIC6_IMMEDIATE_UPDATE, 1);
149149
break;
150150
case 7:
151151
REG_UPDATE(AFMT_VBI_PACKET_CONTROL1,
152-
AFMT_GENERIC7_FRAME_UPDATE, 1);
152+
AFMT_GENERIC7_IMMEDIATE_UPDATE, 1);
153153
break;
154154
default:
155155
break;

‎drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.h

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -281,7 +281,14 @@ struct dcn10_stream_enc_registers {
281281
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_FRAME_UPDATE, mask_sh),\
282282
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_FRAME_UPDATE, mask_sh),\
283283
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_FRAME_UPDATE, mask_sh),\
284+
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC0_IMMEDIATE_UPDATE, mask_sh),\
285+
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC1_IMMEDIATE_UPDATE, mask_sh),\
286+
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC2_IMMEDIATE_UPDATE, mask_sh),\
287+
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC3_IMMEDIATE_UPDATE, mask_sh),\
284288
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC4_IMMEDIATE_UPDATE, mask_sh),\
289+
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_IMMEDIATE_UPDATE, mask_sh),\
290+
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_IMMEDIATE_UPDATE, mask_sh),\
291+
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_IMMEDIATE_UPDATE, mask_sh),\
285292
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC5_FRAME_UPDATE, mask_sh),\
286293
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC6_FRAME_UPDATE, mask_sh),\
287294
SE_SF(DIG0_AFMT_VBI_PACKET_CONTROL1, AFMT_GENERIC7_FRAME_UPDATE, mask_sh),\
@@ -345,7 +352,14 @@ struct dcn10_stream_enc_registers {
345352
type AFMT_GENERIC2_FRAME_UPDATE;\
346353
type AFMT_GENERIC3_FRAME_UPDATE;\
347354
type AFMT_GENERIC4_FRAME_UPDATE;\
355+
type AFMT_GENERIC0_IMMEDIATE_UPDATE;\
356+
type AFMT_GENERIC1_IMMEDIATE_UPDATE;\
357+
type AFMT_GENERIC2_IMMEDIATE_UPDATE;\
358+
type AFMT_GENERIC3_IMMEDIATE_UPDATE;\
348359
type AFMT_GENERIC4_IMMEDIATE_UPDATE;\
360+
type AFMT_GENERIC5_IMMEDIATE_UPDATE;\
361+
type AFMT_GENERIC6_IMMEDIATE_UPDATE;\
362+
type AFMT_GENERIC7_IMMEDIATE_UPDATE;\
349363
type AFMT_GENERIC5_FRAME_UPDATE;\
350364
type AFMT_GENERIC6_FRAME_UPDATE;\
351365
type AFMT_GENERIC7_FRAME_UPDATE;\

‎drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3141,7 +3141,7 @@ static bool dcn20_validate_bandwidth_internal(struct dc *dc, struct dc_state *co
31413141
int vlevel = 0;
31423142
int pipe_split_from[MAX_PIPES];
31433143
int pipe_cnt = 0;
3144-
display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_KERNEL);
3144+
display_e2e_pipe_params_st *pipes = kzalloc(dc->res_pool->pipe_count * sizeof(display_e2e_pipe_params_st), GFP_ATOMIC);
31453145
DC_LOGGER_INIT(dc->ctx->logger);
31463146

31473147
BW_VAL_TRACE_COUNT();

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