Skip to content

Commit 4891b66

Browse files
krzkkwilczynski
krzk
authored and
kwilczynski
committed
dt-bindings: PCI: qcom,pcie-sm8250: Move SM8250 to dedicated schema
Move SM8250 PCIe devices from qcom,pcie.yaml binding to a dedicated file to make reviewing easier. This creates equivalent schema file, except: - Missing required compatible which is actually redundant. - Expecting eight MSI interrupts, instead of only one, which was incomplete hardware description. Link: https://lore.kernel.org/linux-pci/[email protected] Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Krzysztof Wilczyński <[email protected]> Reviewed-by: Rob Herring <[email protected]> Acked-by: Manivannan Sadhasivam <[email protected]>
1 parent 88c9b3a commit 4891b66

File tree

2 files changed

+173
-48
lines changed

2 files changed

+173
-48
lines changed

‎Documentation/devicetree/bindings/pci/qcom,pcie-sm8250.yaml

Lines changed: 173 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,173 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/pci/qcom,pcie-sm8250.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Qualcomm SM8250 PCI Express Root Complex
8+
9+
maintainers:
10+
- Bjorn Andersson <[email protected]>
11+
- Manivannan Sadhasivam <[email protected]>
12+
13+
description:
14+
Qualcomm SM8250 SoC PCIe root complex controller is based on the Synopsys
15+
DesignWare PCIe IP.
16+
17+
properties:
18+
compatible:
19+
const: qcom,pcie-sm8250
20+
21+
reg:
22+
minItems: 5
23+
maxItems: 6
24+
25+
reg-names:
26+
minItems: 5
27+
items:
28+
- const: parf # Qualcomm specific registers
29+
- const: dbi # DesignWare PCIe registers
30+
- const: elbi # External local bus interface registers
31+
- const: atu # ATU address space
32+
- const: config # PCIe configuration space
33+
- const: mhi # MHI registers
34+
35+
clocks:
36+
minItems: 8
37+
maxItems: 9
38+
39+
clock-names:
40+
# Unfortunately the "optional" ref clock is used in the middle of the list
41+
oneOf:
42+
- items:
43+
- const: pipe # PIPE clock
44+
- const: aux # Auxiliary clock
45+
- const: cfg # Configuration clock
46+
- const: bus_master # Master AXI clock
47+
- const: bus_slave # Slave AXI clock
48+
- const: slave_q2a # Slave Q2A clock
49+
- const: ref # REFERENCE clock
50+
- const: tbu # PCIe TBU clock
51+
- const: ddrss_sf_tbu # PCIe SF TBU clock
52+
- items:
53+
- const: pipe # PIPE clock
54+
- const: aux # Auxiliary clock
55+
- const: cfg # Configuration clock
56+
- const: bus_master # Master AXI clock
57+
- const: bus_slave # Slave AXI clock
58+
- const: slave_q2a # Slave Q2A clock
59+
- const: tbu # PCIe TBU clock
60+
- const: ddrss_sf_tbu # PCIe SF TBU clock
61+
62+
interrupts:
63+
minItems: 8
64+
maxItems: 8
65+
66+
interrupt-names:
67+
items:
68+
- const: msi0
69+
- const: msi1
70+
- const: msi2
71+
- const: msi3
72+
- const: msi4
73+
- const: msi5
74+
- const: msi6
75+
- const: msi7
76+
77+
resets:
78+
maxItems: 1
79+
80+
reset-names:
81+
items:
82+
- const: pci
83+
84+
allOf:
85+
- $ref: qcom,pcie-common.yaml#
86+
87+
unevaluatedProperties: false
88+
89+
examples:
90+
- |
91+
#include <dt-bindings/clock/qcom,gcc-sm8250.h>
92+
#include <dt-bindings/gpio/gpio.h>
93+
#include <dt-bindings/interconnect/qcom,sm8250.h>
94+
#include <dt-bindings/interrupt-controller/arm-gic.h>
95+
96+
soc {
97+
#address-cells = <2>;
98+
#size-cells = <2>;
99+
100+
pcie@1c00000 {
101+
compatible = "qcom,pcie-sm8250";
102+
reg = <0 0x01c00000 0 0x3000>,
103+
<0 0x60000000 0 0xf1d>,
104+
<0 0x60000f20 0 0xa8>,
105+
<0 0x60001000 0 0x1000>,
106+
<0 0x60100000 0 0x100000>,
107+
<0 0x01c03000 0 0x1000>;
108+
reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi";
109+
ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
110+
<0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>;
111+
112+
bus-range = <0x00 0xff>;
113+
device_type = "pci";
114+
linux,pci-domain = <0>;
115+
num-lanes = <1>;
116+
117+
#address-cells = <3>;
118+
#size-cells = <2>;
119+
120+
clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
121+
<&gcc GCC_PCIE_0_AUX_CLK>,
122+
<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
123+
<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
124+
<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
125+
<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
126+
<&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>,
127+
<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>;
128+
clock-names = "pipe",
129+
"aux",
130+
"cfg",
131+
"bus_master",
132+
"bus_slave",
133+
"slave_q2a",
134+
"tbu",
135+
"ddrss_sf_tbu";
136+
137+
dma-coherent;
138+
139+
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
140+
<GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
141+
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
142+
<GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
143+
<GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
144+
<GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
145+
<GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
146+
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
147+
interrupt-names = "msi0", "msi1", "msi2", "msi3",
148+
"msi4", "msi5", "msi6", "msi7";
149+
#interrupt-cells = <1>;
150+
interrupt-map-mask = <0 0 0 0x7>;
151+
interrupt-map = <0 0 0 1 &intc 0 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
152+
<0 0 0 2 &intc 0 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
153+
<0 0 0 3 &intc 0 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
154+
<0 0 0 4 &intc 0 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
155+
156+
iommu-map = <0x0 &apps_smmu 0x1c00 0x1>,
157+
<0x100 &apps_smmu 0x1c01 0x1>;
158+
159+
phys = <&pcie0_phy>;
160+
phy-names = "pciephy";
161+
162+
pinctrl-0 = <&pcie0_default_state>;
163+
pinctrl-names = "default";
164+
165+
power-domains = <&gcc PCIE_0_GDSC>;
166+
167+
resets = <&gcc GCC_PCIE_0_BCR>;
168+
reset-names = "pci";
169+
170+
perst-gpios = <&tlmm 79 GPIO_ACTIVE_LOW>;
171+
wake-gpios = <&tlmm 81 GPIO_ACTIVE_HIGH>;
172+
};
173+
};

‎Documentation/devicetree/bindings/pci/qcom,pcie.yaml

Lines changed: 0 additions & 48 deletions
Original file line numberDiff line numberDiff line change
@@ -36,7 +36,6 @@ properties:
3636
- qcom,pcie-sdm845
3737
- qcom,pcie-sdx55
3838
- qcom,pcie-sm8150
39-
- qcom,pcie-sm8250
4039
- qcom,pcie-sm8350
4140
- items:
4241
- const: qcom,pcie-msm8998
@@ -215,7 +214,6 @@ allOf:
215214
- qcom,pcie-sc8180x
216215
- qcom,pcie-sc8280xp
217216
- qcom,pcie-sdx55
218-
- qcom,pcie-sm8250
219217
- qcom,pcie-sm8350
220218
then:
221219
properties:
@@ -570,51 +568,6 @@ allOf:
570568
items:
571569
- const: pci # PCIe core reset
572570

573-
- if:
574-
properties:
575-
compatible:
576-
contains:
577-
enum:
578-
- qcom,pcie-sm8250
579-
then:
580-
oneOf:
581-
# Unfortunately the "optional" ref clock is used in the middle of the list
582-
- properties:
583-
clocks:
584-
minItems: 9
585-
maxItems: 9
586-
clock-names:
587-
items:
588-
- const: pipe # PIPE clock
589-
- const: aux # Auxiliary clock
590-
- const: cfg # Configuration clock
591-
- const: bus_master # Master AXI clock
592-
- const: bus_slave # Slave AXI clock
593-
- const: slave_q2a # Slave Q2A clock
594-
- const: ref # REFERENCE clock
595-
- const: tbu # PCIe TBU clock
596-
- const: ddrss_sf_tbu # PCIe SF TBU clock
597-
- properties:
598-
clocks:
599-
minItems: 8
600-
maxItems: 8
601-
clock-names:
602-
items:
603-
- const: pipe # PIPE clock
604-
- const: aux # Auxiliary clock
605-
- const: cfg # Configuration clock
606-
- const: bus_master # Master AXI clock
607-
- const: bus_slave # Slave AXI clock
608-
- const: slave_q2a # Slave Q2A clock
609-
- const: tbu # PCIe TBU clock
610-
- const: ddrss_sf_tbu # PCIe SF TBU clock
611-
properties:
612-
resets:
613-
maxItems: 1
614-
reset-names:
615-
items:
616-
- const: pci # PCIe core reset
617-
618571
- if:
619572
properties:
620573
compatible:
@@ -777,7 +730,6 @@ allOf:
777730
- qcom,pcie-sc8180x
778731
- qcom,pcie-sdm845
779732
- qcom,pcie-sm8150
780-
- qcom,pcie-sm8250
781733
- qcom,pcie-sm8350
782734
then:
783735
oneOf:

0 commit comments

Comments
 (0)