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Dinh Nguyen
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arm64: dts: agilex: populate clock dts entries for Intel SoCFPGA Agilex
Add clock dts entries to the Intel SoCFPGA Agilex platform. Signed-off-by: Dinh Nguyen <[email protected]>
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‎arch/arm64/boot/dts/intel/socfpga_agilex.dtsi

Lines changed: 73 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,7 @@
66
/dts-v1/;
77
#include <dt-bindings/reset/altr,rst-mgr-s10.h>
88
#include <dt-bindings/gpio/gpio.h>
9+
#include <dt-bindings/clock/agilex-clock.h>
910

1011
/ {
1112
compatible = "intel,socfpga-agilex";
@@ -101,6 +102,40 @@
101102
fpga-mgr = <&fpga_mgr>;
102103
};
103104

105+
clkmgr: clock-controller@ffd10000 {
106+
compatible = "intel,agilex-clkmgr";
107+
reg = <0xffd10000 0x1000>;
108+
#clock-cells = <1>;
109+
};
110+
111+
clocks {
112+
cb_intosc_hs_div2_clk: cb-intosc-hs-div2-clk {
113+
#clock-cells = <0>;
114+
compatible = "fixed-clock";
115+
};
116+
117+
cb_intosc_ls_clk: cb-intosc-ls-clk {
118+
#clock-cells = <0>;
119+
compatible = "fixed-clock";
120+
};
121+
122+
f2s_free_clk: f2s-free-clk {
123+
#clock-cells = <0>;
124+
compatible = "fixed-clock";
125+
};
126+
127+
osc1: osc1 {
128+
#clock-cells = <0>;
129+
compatible = "fixed-clock";
130+
};
131+
132+
qspi_clk: qspi-clk {
133+
#clock-cells = <0>;
134+
compatible = "fixed-clock";
135+
clock-frequency = <200000000>;
136+
};
137+
};
138+
104139
gmac0: ethernet@ff800000 {
105140
compatible = "altr,socfpga-stmmac-a10-s10", "snps,dwmac-3.74a", "snps,dwmac";
106141
reg = <0xff800000 0x2000>;
@@ -114,6 +149,8 @@
114149
snps,multicast-filter-bins = <256>;
115150
iommus = <&smmu 1>;
116151
altr,sysmgr-syscon = <&sysmgr 0x44 0>;
152+
clocks = <&clkmgr AGILEX_EMAC0_CLK>;
153+
clock-names = "stmmaceth";
117154
status = "disabled";
118155
};
119156

@@ -130,6 +167,8 @@
130167
snps,multicast-filter-bins = <256>;
131168
iommus = <&smmu 2>;
132169
altr,sysmgr-syscon = <&sysmgr 0x48 8>;
170+
clocks = <&clkmgr AGILEX_EMAC1_CLK>;
171+
clock-names = "stmmaceth";
133172
status = "disabled";
134173
};
135174

@@ -146,6 +185,8 @@
146185
snps,multicast-filter-bins = <256>;
147186
iommus = <&smmu 3>;
148187
altr,sysmgr-syscon = <&sysmgr 0x4c 16>;
188+
clocks = <&clkmgr AGILEX_EMAC2_CLK>;
189+
clock-names = "stmmaceth";
149190
status = "disabled";
150191
};
151192

@@ -196,6 +237,7 @@
196237
reg = <0xffc02800 0x100>;
197238
interrupts = <0 103 4>;
198239
resets = <&rst I2C0_RESET>;
240+
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
199241
status = "disabled";
200242
};
201243

@@ -206,6 +248,7 @@
206248
reg = <0xffc02900 0x100>;
207249
interrupts = <0 104 4>;
208250
resets = <&rst I2C1_RESET>;
251+
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
209252
status = "disabled";
210253
};
211254

@@ -216,6 +259,7 @@
216259
reg = <0xffc02a00 0x100>;
217260
interrupts = <0 105 4>;
218261
resets = <&rst I2C2_RESET>;
262+
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
219263
status = "disabled";
220264
};
221265

@@ -226,6 +270,7 @@
226270
reg = <0xffc02b00 0x100>;
227271
interrupts = <0 106 4>;
228272
resets = <&rst I2C3_RESET>;
273+
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
229274
status = "disabled";
230275
};
231276

@@ -236,6 +281,7 @@
236281
reg = <0xffc02c00 0x100>;
237282
interrupts = <0 107 4>;
238283
resets = <&rst I2C4_RESET>;
284+
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
239285
status = "disabled";
240286
};
241287

@@ -248,6 +294,9 @@
248294
fifo-depth = <0x400>;
249295
resets = <&rst SDMMC_RESET>;
250296
reset-names = "reset";
297+
clocks = <&clkmgr AGILEX_L4_MP_CLK>,
298+
<&clkmgr AGILEX_SDMMC_CLK>;
299+
clock-names = "biu", "ciu";
251300
iommus = <&smmu 5>;
252301
status = "disabled";
253302
};
@@ -286,6 +335,8 @@
286335
#dma-requests = <32>;
287336
resets = <&rst DMA_RESET>, <&rst DMA_OCP_RESET>;
288337
reset-names = "dma", "dma-ocp";
338+
clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
339+
clock-names = "apb_pclk";
289340
};
290341

291342
rst: rstmgr@ffd11000 {
@@ -312,6 +363,9 @@
312363
<0 162 4>, <0 163 4>, <0 164 4>, <0 165 4>,
313364
<0 166 4>, <0 167 4>, <0 168 4>, <0 169 4>;
314365
stream-match-mask = <0x7ff0>;
366+
clocks = <&clkmgr AGILEX_MPU_CCU_CLK>,
367+
<&clkmgr AGILEX_L3_MAIN_FREE_CLK>,
368+
<&clkmgr AGILEX_L4_MAIN_CLK>;
315369
status = "disabled";
316370
};
317371

@@ -324,6 +378,7 @@
324378
resets = <&rst SPIM0_RESET>;
325379
reg-io-width = <4>;
326380
num-cs = <4>;
381+
clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
327382
status = "disabled";
328383
};
329384

@@ -336,6 +391,7 @@
336391
resets = <&rst SPIM1_RESET>;
337392
reg-io-width = <4>;
338393
num-cs = <4>;
394+
clocks = <&clkmgr AGILEX_L4_MAIN_CLK>;
339395
status = "disabled";
340396
};
341397

@@ -357,24 +413,32 @@
357413
compatible = "snps,dw-apb-timer";
358414
interrupts = <0 113 4>;
359415
reg = <0xffc03000 0x100>;
416+
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
417+
clock-names = "timer";
360418
};
361419

362420
timer1: timer1@ffc03100 {
363421
compatible = "snps,dw-apb-timer";
364422
interrupts = <0 114 4>;
365423
reg = <0xffc03100 0x100>;
424+
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
425+
clock-names = "timer";
366426
};
367427

368428
timer2: timer2@ffd00000 {
369429
compatible = "snps,dw-apb-timer";
370430
interrupts = <0 115 4>;
371431
reg = <0xffd00000 0x100>;
432+
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
433+
clock-names = "timer";
372434
};
373435

374436
timer3: timer3@ffd00100 {
375437
compatible = "snps,dw-apb-timer";
376438
interrupts = <0 116 4>;
377439
reg = <0xffd00100 0x100>;
440+
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
441+
clock-names = "timer";
378442
};
379443

380444
uart0: serial0@ffc02000 {
@@ -385,6 +449,7 @@
385449
reg-io-width = <4>;
386450
resets = <&rst UART0_RESET>;
387451
status = "disabled";
452+
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
388453
};
389454

390455
uart1: serial1@ffc02100 {
@@ -394,6 +459,7 @@
394459
reg-shift = <2>;
395460
reg-io-width = <4>;
396461
resets = <&rst UART1_RESET>;
462+
clocks = <&clkmgr AGILEX_L4_SP_CLK>;
397463
status = "disabled";
398464
};
399465

@@ -411,6 +477,7 @@
411477
phy-names = "usb2-phy";
412478
resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>;
413479
reset-names = "dwc2", "dwc2-ecc";
480+
clocks = <&clkmgr AGILEX_USB_CLK>;
414481
iommus = <&smmu 6>;
415482
status = "disabled";
416483
};
@@ -424,6 +491,7 @@
424491
resets = <&rst USB1_RESET>, <&rst USB1_OCP_RESET>;
425492
reset-names = "dwc2", "dwc2-ecc";
426493
iommus = <&smmu 7>;
494+
clocks = <&clkmgr AGILEX_USB_CLK>;
427495
status = "disabled";
428496
};
429497

@@ -432,6 +500,7 @@
432500
reg = <0xffd00200 0x100>;
433501
interrupts = <0 117 4>;
434502
resets = <&rst WATCHDOG0_RESET>;
503+
clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
435504
status = "disabled";
436505
};
437506

@@ -440,6 +509,7 @@
440509
reg = <0xffd00300 0x100>;
441510
interrupts = <0 118 4>;
442511
resets = <&rst WATCHDOG1_RESET>;
512+
clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
443513
status = "disabled";
444514
};
445515

@@ -448,6 +518,7 @@
448518
reg = <0xffd00400 0x100>;
449519
interrupts = <0 125 4>;
450520
resets = <&rst WATCHDOG2_RESET>;
521+
clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
451522
status = "disabled";
452523
};
453524

@@ -456,6 +527,7 @@
456527
reg = <0xffd00500 0x100>;
457528
interrupts = <0 126 4>;
458529
resets = <&rst WATCHDOG3_RESET>;
530+
clocks = <&clkmgr AGILEX_L4_SYS_FREE_CLK>;
459531
status = "disabled";
460532
};
461533

@@ -533,6 +605,7 @@
533605
cdns,fifo-depth = <128>;
534606
cdns,fifo-width = <4>;
535607
cdns,trigger-address = <0x00000000>;
608+
clocks = <&qspi_clk>;
536609

537610
status = "disabled";
538611
};

‎arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,14 @@
4141
/* We expect the bootloader to fill in the reg */
4242
reg = <0 0 0 0>;
4343
};
44+
45+
soc {
46+
clocks {
47+
osc1 {
48+
clock-frequency = <25000000>;
49+
};
50+
};
51+
};
4452
};
4553

4654
&gpio1 {

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