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perf vendor events amd: Fix Zen 4 cache latency events
L3PMCx0AC and L3PMCx0AD, used in l3_xi_sampled_latency* events, have a quirk that requires them to be programmed with SliceId set to 0x3. Without this, the events do not count at all and affects dependent metrics such as l3_read_miss_latency. If ThreadMask is not specified, the amd-uncore driver internally sets ThreadMask to 0x3, EnAllCores to 0x1 and EnAllSlices to 0x1 but does not set SliceId. Since SliceId must also be set to 0x3 in this case, specify all the other fields explicitly. E.g. $ sudo perf stat -e l3_xi_sampled_latency.all,l3_xi_sampled_latency_requests.all -a sleep 1 Before: Performance counter stats for 'system wide': 0 l3_xi_sampled_latency.all 0 l3_xi_sampled_latency_requests.all 1.005155399 seconds time elapsed After: Performance counter stats for 'system wide': 921,446 l3_xi_sampled_latency.all 54,210 l3_xi_sampled_latency_requests.all 1.005664472 seconds time elapsed Fixes: 5b2ca34 ("perf vendor events amd: Add Zen 4 uncore events") Signed-off-by: Sandipan Das <[email protected]> Reviewed-by: Ian Rogers <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Signed-off-by: Namhyung Kim <[email protected]> Link: https://lore.kernel.org/r/[email protected]
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‎tools/perf/pmu-events/arch/x86/amdzen4/cache.json

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@@ -676,97 +676,153 @@
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency when data is sourced from DRAM in the same NUMA node.",
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"UMask": "0x01",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.dram_far",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency when data is sourced from DRAM in a different NUMA node.",
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"UMask": "0x02",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.near_cache",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in the same NUMA node.",
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"UMask": "0x04",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.far_cache",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in a different NUMA node.",
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"UMask": "0x08",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.ext_near",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in the same NUMA node.",
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"UMask": "0x10",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.ext_far",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in a different NUMA node.",
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"UMask": "0x20",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.all",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency from all data sources.",
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"UMask": "0x3f",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.dram_near",
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"EventCode": "0xad",
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"BriefDescription": "L3 cache fill requests sourced from DRAM in the same NUMA node.",
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"UMask": "0x01",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.dram_far",
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"EventCode": "0xad",
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"BriefDescription": "L3 cache fill requests sourced from DRAM in a different NUMA node.",
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"UMask": "0x02",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.near_cache",
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"EventCode": "0xad",
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"BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in the same NUMA node.",
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"UMask": "0x04",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.far_cache",
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"EventCode": "0xad",
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"BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in a different NUMA node.",
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"UMask": "0x08",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.ext_near",
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"EventCode": "0xad",
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"BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in the same NUMA node.",
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"UMask": "0x10",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.ext_far",
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"EventCode": "0xad",
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"BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in a different NUMA node.",
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"UMask": "0x20",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.all",
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"EventCode": "0xad",
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"BriefDescription": "L3 cache fill requests sourced from all data sources.",
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"UMask": "0x3f",
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"EnAllCores": "0x1",
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"EnAllSlices": "0x1",
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"SliceId": "0x3",
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"ThreadMask": "0x3",
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"Unit": "L3PMC"
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}
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]

‎tools/perf/pmu-events/jevents.py

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@@ -373,6 +373,10 @@ def canonicalize_value(val: str) -> str:
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('UMask', 'umask='),
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('NodeType', 'type='),
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('RdWrMask', 'rdwrmask='),
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('EnAllCores', 'enallcores='),
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('EnAllSlices', 'enallslices='),
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('SliceId', 'sliceid='),
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('ThreadMask', 'threadmask='),
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]
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for key, value in event_fields:
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if key in jd and not is_zero(jd[key]):

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