@@ -29,31 +29,6 @@ static const struct pci_device_id amd_nb_misc_ids[] = {
29
29
{ PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_15H_M60H_NB_F3 ) },
30
30
{ PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_16H_NB_F3 ) },
31
31
{ PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_16H_M30H_NB_F3 ) },
32
- { PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_17H_DF_F3 ) },
33
- { PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_17H_M10H_DF_F3 ) },
34
- { PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_17H_M30H_DF_F3 ) },
35
- { PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_17H_M60H_DF_F3 ) },
36
- { PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_17H_MA0H_DF_F3 ) },
37
- { PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_CNB17H_F3 ) },
38
- { PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_17H_M70H_DF_F3 ) },
39
- { PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_19H_DF_F3 ) },
40
- { PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_19H_M10H_DF_F3 ) },
41
- { PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_19H_M40H_DF_F3 ) },
42
- { PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_19H_M50H_DF_F3 ) },
43
- { PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_19H_M60H_DF_F3 ) },
44
- { PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_19H_M70H_DF_F3 ) },
45
- { PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_19H_M78H_DF_F3 ) },
46
- { PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_1AH_M00H_DF_F3 ) },
47
- { PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_1AH_M20H_DF_F3 ) },
48
- { PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_1AH_M60H_DF_F3 ) },
49
- { PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_1AH_M70H_DF_F3 ) },
50
- { PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_MI200_DF_F3 ) },
51
- { PCI_DEVICE (PCI_VENDOR_ID_AMD , PCI_DEVICE_ID_AMD_MI300_DF_F3 ) },
52
- {}
53
- };
54
-
55
- static const struct pci_device_id hygon_nb_misc_ids [] = {
56
- { PCI_DEVICE (PCI_VENDOR_ID_HYGON , PCI_DEVICE_ID_AMD_17H_DF_F3 ) },
57
32
{}
58
33
};
59
34
@@ -84,17 +59,6 @@ struct amd_northbridge *node_to_amd_nb(int node)
84
59
}
85
60
EXPORT_SYMBOL_GPL (node_to_amd_nb );
86
61
87
- static struct pci_dev * next_northbridge (struct pci_dev * dev ,
88
- const struct pci_device_id * ids )
89
- {
90
- do {
91
- dev = pci_get_device (PCI_ANY_ID , PCI_ANY_ID , dev );
92
- if (!dev )
93
- break ;
94
- } while (!pci_match_id (ids , dev ));
95
- return dev ;
96
- }
97
-
98
62
/*
99
63
* SMN accesses may fail in ways that are difficult to detect here in the called
100
64
* functions amd_smn_read() and amd_smn_write(). Therefore, callers must do
@@ -183,18 +147,12 @@ EXPORT_SYMBOL_GPL(amd_smn_write);
183
147
184
148
static int amd_cache_northbridges (void )
185
149
{
186
- const struct pci_device_id * misc_ids = amd_nb_misc_ids ;
187
- struct pci_dev * misc ;
188
150
struct amd_northbridge * nb ;
189
151
u16 i ;
190
152
191
153
if (amd_northbridges .num )
192
154
return 0 ;
193
155
194
- if (boot_cpu_data .x86_vendor == X86_VENDOR_HYGON ) {
195
- misc_ids = hygon_nb_misc_ids ;
196
- }
197
-
198
156
amd_northbridges .num = amd_num_nodes ();
199
157
200
158
nb = kcalloc (amd_northbridges .num , sizeof (struct amd_northbridge ), GFP_KERNEL );
@@ -203,11 +161,9 @@ static int amd_cache_northbridges(void)
203
161
204
162
amd_northbridges .nb = nb ;
205
163
206
- misc = NULL ;
207
164
for (i = 0 ; i < amd_northbridges .num ; i ++ ) {
208
165
node_to_amd_nb (i )-> root = amd_node_get_root (i );
209
- node_to_amd_nb (i )-> misc = misc =
210
- next_northbridge (misc , misc_ids );
166
+ node_to_amd_nb (i )-> misc = amd_node_get_func (i , 3 );
211
167
212
168
/*
213
169
* Each Northbridge must have a 'misc' device.
0 commit comments