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Merge tag 'perf-tools-fixes-for-v6.3-1-2023-03-09' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux
Pull perf tools fixes from Arnaldo Carvalho de Melo: - Add Adrian Hunter to MAINTAINERS as a perf tools reviewer - Sync various tools/ copies of kernel headers with the kernel sources, this time trying to avoid first merging with upstream to then update but instead copy from upstream so that a merge is avoided and the end result after merging this pull request is the one expected, tools/perf/check-headers.sh (mostly) happy, less warnings while building tools/perf/ - Fix counting when initial delay configured by setting perf_attr.enable_on_exec when starting workloads from the perf command line - Don't avoid emitting a PERF_RECORD_MMAP2 in 'perf inject --buildid-all' when that record comes with a build-id, otherwise we end up not being able to resolve symbols - Don't use comma as the CSV output separator the "stat+csv_output" test, as comma can appear on some tests as a modifier for an event, use @ instead, ditto for the JSON linter test - The offcpu test was looking for some bits being set on task_struct->prev_state without masking other bits not important for this specific 'perf test', fix it * tag 'perf-tools-fixes-for-v6.3-1-2023-03-09' of git://git.kernel.org/pub/scm/linux/kernel/git/acme/linux: perf tools: Add Adrian Hunter to MAINTAINERS as a reviewer tools headers UAPI: Sync linux/perf_event.h with the kernel sources tools headers x86 cpufeatures: Sync with the kernel sources tools include UAPI: Sync linux/vhost.h with the kernel sources tools arch x86: Sync the msr-index.h copy with the kernel sources tools headers kvm: Sync uapi/{asm/linux} kvm.h headers with the kernel sources tools include UAPI: Synchronize linux/fcntl.h with the kernel sources tools headers: Synchronize {linux,vdso}/bits.h with the kernel sources tools headers UAPI: Sync linux/prctl.h with the kernel sources tools headers: Update the copy of x86's mem{cpy,set}_64.S used in 'perf bench' perf stat: Fix counting when initial delay configured tools headers svm: Sync svm headers with the kernel sources perf test: Avoid counting commas in json linter perf tests stat+csv_output: Switch CSV separator to @ perf inject: Fix --buildid-all not to eat up MMAP2 tools arch x86: Sync the msr-index.h copy with the kernel sources perf test: Fix offcpu test prev_state check
2 parents 44889ba + 5b201a8 commit 49be4fb

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MAINTAINERS

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@@ -16391,6 +16391,7 @@ R: Alexander Shishkin <[email protected]>
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R: Jiri Olsa <[email protected]>
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R: Namhyung Kim <[email protected]>
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R: Ian Rogers <[email protected]>
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R: Adrian Hunter <[email protected]>
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1639516396
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S: Supported

tools/arch/arm64/include/uapi/asm/kvm.h

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@@ -109,6 +109,7 @@ struct kvm_regs {
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#define KVM_ARM_VCPU_SVE 4 /* enable SVE for this CPU */
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#define KVM_ARM_VCPU_PTRAUTH_ADDRESS 5 /* VCPU uses address authentication */
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#define KVM_ARM_VCPU_PTRAUTH_GENERIC 6 /* VCPU uses generic authentication */
112+
#define KVM_ARM_VCPU_HAS_EL2 7 /* Support nested virtualization */
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struct kvm_vcpu_init {
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__u32 target;

tools/arch/x86/include/asm/cpufeatures.h

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@@ -13,7 +13,7 @@
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/*
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* Defines x86 CPU feature bits
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*/
16-
#define NCAPINTS 20 /* N 32-bit words worth of info */
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#define NCAPINTS 21 /* N 32-bit words worth of info */
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#define NBUGINTS 1 /* N 32-bit bug flags */
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1919
/*

tools/arch/x86/include/asm/disabled-features.h

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@@ -124,6 +124,7 @@
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#define DISABLED_MASK17 0
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#define DISABLED_MASK18 0
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#define DISABLED_MASK19 0
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#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20)
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#define DISABLED_MASK20 0
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#define DISABLED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 21)
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#endif /* _ASM_X86_DISABLED_FEATURES_H */

tools/arch/x86/include/asm/msr-index.h

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@@ -25,6 +25,7 @@
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#define _EFER_SVME 12 /* Enable virtualization */
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#define _EFER_LMSLE 13 /* Long Mode Segment Limit Enable */
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#define _EFER_FFXSR 14 /* Enable Fast FXSAVE/FXRSTOR */
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#define _EFER_AUTOIBRS 21 /* Enable Automatic IBRS */
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#define EFER_SCE (1<<_EFER_SCE)
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#define EFER_LME (1<<_EFER_LME)
@@ -33,6 +34,7 @@
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#define EFER_SVME (1<<_EFER_SVME)
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#define EFER_LMSLE (1<<_EFER_LMSLE)
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#define EFER_FFXSR (1<<_EFER_FFXSR)
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#define EFER_AUTOIBRS (1<<_EFER_AUTOIBRS)
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/* Intel MSRs. Some also available on other CPUs */
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@@ -49,6 +51,10 @@
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#define SPEC_CTRL_RRSBA_DIS_S_SHIFT 6 /* Disable RRSBA behavior */
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#define SPEC_CTRL_RRSBA_DIS_S BIT(SPEC_CTRL_RRSBA_DIS_S_SHIFT)
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54+
/* A mask for bits which the kernel toggles when controlling mitigations */
55+
#define SPEC_CTRL_MITIGATIONS_MASK (SPEC_CTRL_IBRS | SPEC_CTRL_STIBP | SPEC_CTRL_SSBD \
56+
| SPEC_CTRL_RRSBA_DIS_S)
57+
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#define MSR_IA32_PRED_CMD 0x00000049 /* Prediction Command */
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#define PRED_CMD_IBPB BIT(0) /* Indirect Branch Prediction Barrier */
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@@ -189,6 +195,9 @@
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#define MSR_TURBO_RATIO_LIMIT1 0x000001ae
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#define MSR_TURBO_RATIO_LIMIT2 0x000001af
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198+
#define MSR_SNOOP_RSP_0 0x00001328
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#define MSR_SNOOP_RSP_1 0x00001329
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#define MSR_LBR_SELECT 0x000001c8
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#define MSR_LBR_TOS 0x000001c9
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@@ -566,6 +575,26 @@
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#define MSR_AMD64_SEV_ES_ENABLED BIT_ULL(MSR_AMD64_SEV_ES_ENABLED_BIT)
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#define MSR_AMD64_SEV_SNP_ENABLED BIT_ULL(MSR_AMD64_SEV_SNP_ENABLED_BIT)
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578+
/* SNP feature bits enabled by the hypervisor */
579+
#define MSR_AMD64_SNP_VTOM BIT_ULL(3)
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#define MSR_AMD64_SNP_REFLECT_VC BIT_ULL(4)
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#define MSR_AMD64_SNP_RESTRICTED_INJ BIT_ULL(5)
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#define MSR_AMD64_SNP_ALT_INJ BIT_ULL(6)
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#define MSR_AMD64_SNP_DEBUG_SWAP BIT_ULL(7)
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#define MSR_AMD64_SNP_PREVENT_HOST_IBS BIT_ULL(8)
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#define MSR_AMD64_SNP_BTB_ISOLATION BIT_ULL(9)
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#define MSR_AMD64_SNP_VMPL_SSS BIT_ULL(10)
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#define MSR_AMD64_SNP_SECURE_TSC BIT_ULL(11)
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#define MSR_AMD64_SNP_VMGEXIT_PARAM BIT_ULL(12)
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#define MSR_AMD64_SNP_IBS_VIRT BIT_ULL(14)
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#define MSR_AMD64_SNP_VMSA_REG_PROTECTION BIT_ULL(16)
591+
#define MSR_AMD64_SNP_SMT_PROTECTION BIT_ULL(17)
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/* SNP feature bits reserved for future use. */
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#define MSR_AMD64_SNP_RESERVED_BIT13 BIT_ULL(13)
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#define MSR_AMD64_SNP_RESERVED_BIT15 BIT_ULL(15)
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#define MSR_AMD64_SNP_RESERVED_MASK GENMASK_ULL(63, 18)
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#define MSR_AMD64_VIRT_SPEC_CTRL 0xc001011f
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/* AMD Collaborative Processor Performance Control MSRs */
@@ -1061,6 +1090,8 @@
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/* - AMD: */
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#define MSR_IA32_MBA_BW_BASE 0xc0000200
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#define MSR_IA32_SMBA_BW_BASE 0xc0000280
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#define MSR_IA32_EVT_CFG_BASE 0xc0000400
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/* MSR_IA32_VMX_MISC bits */
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#define MSR_IA32_VMX_MISC_INTEL_PT (1ULL << 14)

tools/arch/x86/include/asm/required-features.h

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@@ -98,6 +98,7 @@
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#define REQUIRED_MASK17 0
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#define REQUIRED_MASK18 0
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#define REQUIRED_MASK19 0
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#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 20)
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#define REQUIRED_MASK20 0
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#define REQUIRED_MASK_CHECK BUILD_BUG_ON_ZERO(NCAPINTS != 21)
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#endif /* _ASM_X86_REQUIRED_FEATURES_H */

tools/arch/x86/include/uapi/asm/kvm.h

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@@ -9,6 +9,7 @@
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#include <linux/types.h>
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#include <linux/ioctl.h>
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#include <linux/stddef.h>
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#define KVM_PIO_PAGE_OFFSET 1
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#define KVM_COALESCED_MMIO_PAGE_OFFSET 2
@@ -507,8 +508,8 @@ struct kvm_nested_state {
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* KVM_{GET,PUT}_NESTED_STATE ioctl values.
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*/
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union {
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struct kvm_vmx_nested_state_data vmx[0];
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struct kvm_svm_nested_state_data svm[0];
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__DECLARE_FLEX_ARRAY(struct kvm_vmx_nested_state_data, vmx);
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__DECLARE_FLEX_ARRAY(struct kvm_svm_nested_state_data, svm);
512513
} data;
513514
};
514515

@@ -525,6 +526,35 @@ struct kvm_pmu_event_filter {
525526
#define KVM_PMU_EVENT_ALLOW 0
526527
#define KVM_PMU_EVENT_DENY 1
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529+
#define KVM_PMU_EVENT_FLAG_MASKED_EVENTS BIT(0)
530+
#define KVM_PMU_EVENT_FLAGS_VALID_MASK (KVM_PMU_EVENT_FLAG_MASKED_EVENTS)
531+
532+
/*
533+
* Masked event layout.
534+
* Bits Description
535+
* ---- -----------
536+
* 7:0 event select (low bits)
537+
* 15:8 umask match
538+
* 31:16 unused
539+
* 35:32 event select (high bits)
540+
* 36:54 unused
541+
* 55 exclude bit
542+
* 63:56 umask mask
543+
*/
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545+
#define KVM_PMU_ENCODE_MASKED_ENTRY(event_select, mask, match, exclude) \
546+
(((event_select) & 0xFFULL) | (((event_select) & 0XF00ULL) << 24) | \
547+
(((mask) & 0xFFULL) << 56) | \
548+
(((match) & 0xFFULL) << 8) | \
549+
((__u64)(!!(exclude)) << 55))
550+
551+
#define KVM_PMU_MASKED_ENTRY_EVENT_SELECT \
552+
(GENMASK_ULL(7, 0) | GENMASK_ULL(35, 32))
553+
#define KVM_PMU_MASKED_ENTRY_UMASK_MASK (GENMASK_ULL(63, 56))
554+
#define KVM_PMU_MASKED_ENTRY_UMASK_MATCH (GENMASK_ULL(15, 8))
555+
#define KVM_PMU_MASKED_ENTRY_EXCLUDE (BIT_ULL(55))
556+
#define KVM_PMU_MASKED_ENTRY_UMASK_MASK_SHIFT (56)
557+
528558
/* for KVM_{GET,SET,HAS}_DEVICE_ATTR */
529559
#define KVM_VCPU_TSC_CTRL 0 /* control group for the timestamp counter (TSC) */
530560
#define KVM_VCPU_TSC_OFFSET 0 /* attribute for the TSC offset */

tools/arch/x86/include/uapi/asm/svm.h

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@@ -116,6 +116,12 @@
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#define SVM_VMGEXIT_AP_CREATE 1
117117
#define SVM_VMGEXIT_AP_DESTROY 2
118118
#define SVM_VMGEXIT_HV_FEATURES 0x8000fffd
119+
#define SVM_VMGEXIT_TERM_REQUEST 0x8000fffe
120+
#define SVM_VMGEXIT_TERM_REASON(reason_set, reason_code) \
121+
/* SW_EXITINFO1[3:0] */ \
122+
(((((u64)reason_set) & 0xf)) | \
123+
/* SW_EXITINFO1[11:4] */ \
124+
((((u64)reason_code) & 0xff) << 4))
119125
#define SVM_VMGEXIT_UNSUPPORTED_EVENT 0x8000ffff
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121127
/* Exit code reserved for hypervisor/software use */

tools/arch/x86/lib/memcpy_64.S

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@@ -7,7 +7,7 @@
77
#include <asm/alternative.h>
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#include <asm/export.h>
99

10-
.pushsection .noinstr.text, "ax"
10+
.section .noinstr.text, "ax"
1111

1212
/*
1313
* We build a jump to memcpy_orig by default which gets NOPped out on
@@ -42,7 +42,7 @@ SYM_TYPED_FUNC_START(__memcpy)
4242
SYM_FUNC_END(__memcpy)
4343
EXPORT_SYMBOL(__memcpy)
4444

45-
SYM_FUNC_ALIAS_WEAK(memcpy, __memcpy)
45+
SYM_FUNC_ALIAS(memcpy, __memcpy)
4646
EXPORT_SYMBOL(memcpy)
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4848
/*
@@ -183,4 +183,3 @@ SYM_FUNC_START_LOCAL(memcpy_orig)
183183
RET
184184
SYM_FUNC_END(memcpy_orig)
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186-
.popsection

tools/arch/x86/lib/memset_64.S

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@@ -6,6 +6,8 @@
66
#include <asm/alternative.h>
77
#include <asm/export.h>
88

9+
.section .noinstr.text, "ax"
10+
911
/*
1012
* ISO C memset - set a memory block to a byte value. This function uses fast
1113
* string to get better performance than the original function. The code is
@@ -43,7 +45,7 @@ SYM_FUNC_START(__memset)
4345
SYM_FUNC_END(__memset)
4446
EXPORT_SYMBOL(__memset)
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46-
SYM_FUNC_ALIAS_WEAK(memset, __memset)
48+
SYM_FUNC_ALIAS(memset, __memset)
4749
EXPORT_SYMBOL(memset)
4850

4951
/*

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