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Merge 5.17-rc6 into driver-core-next
We need the driver core fix in here as well for future changes. Signed-off-by: Greg Kroah-Hartman <[email protected]>
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.mailmap

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@@ -70,6 +70,7 @@ Boris Brezillon <[email protected]> <[email protected]>
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Brian Avery <[email protected]>
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Brian King <[email protected]>
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@@ -79,6 +80,9 @@ Chris Chiu <[email protected]> <[email protected]>
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Christian Borntraeger <[email protected]> <[email protected]>
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Christian Borntraeger <[email protected]> <[email protected]>
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Christian Borntraeger <[email protected]> <[email protected]>
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Christophe Ricard <[email protected]>
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Christoph Hellwig <[email protected]>
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@@ -329,6 +333,9 @@ Rémi Denis-Courmont <[email protected]>
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Ricardo Ribalda <[email protected]> Ricardo Ribalda Delgado <[email protected]>
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Rudolf Marek <[email protected]>
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Rui Saraiva <[email protected]>

Documentation/ABI/testing/sysfs-class-power

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auto: Charge normally, respect thresholds
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inhibit-charge: Do not charge while AC is attached
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force-discharge: Force discharge while AC is attached
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================ ====================================
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What: /sys/class/power_supply/<supply_name>/technology
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Date: May 2007

Documentation/ABI/testing/sysfs-driver-aspeed-uart-routing

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What: /sys/bus/platform/drivers/aspeed-uart-routing/*/uart*
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What: /sys/bus/platform/drivers/aspeed-uart-routing/\*/uart\*
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Date: September 2021
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Contact: Oskar Senft <[email protected]>
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Chia-Wei Wang <[email protected]>
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depends on the selected file.
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e.g.
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cat /sys/bus/platform/drivers/aspeed-uart-routing/*.uart_routing/uart1
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cat /sys/bus/platform/drivers/aspeed-uart-routing/\*.uart_routing/uart1
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[io1] io2 io3 io4 uart2 uart3 uart4 io6
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In this case, UART1 gets its input from IO1 (physical serial port 1).
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Users: OpenBMC. Proposed changes should be mailed to
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What: /sys/bus/platform/drivers/aspeed-uart-routing/*/io*
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What: /sys/bus/platform/drivers/aspeed-uart-routing/\*/io\*
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Date: September 2021
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Contact: Oskar Senft <[email protected]>
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Chia-Wei Wang <[email protected]>

Documentation/accounting/psi.rst

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@@ -92,7 +92,8 @@ Triggers can be set on more than one psi metric and more than one trigger
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for the same psi metric can be specified. However for each trigger a separate
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file descriptor is required to be able to poll it separately from others,
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therefore for each trigger a separate open() syscall should be made even
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when opening the same psi interface file.
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when opening the same psi interface file. Write operations to a file descriptor
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with an already existing psi trigger will fail with EBUSY.
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Monitors activate only when system enters stall state for the monitored
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psi metric and deactivates upon exit from the stall state. While system is

Documentation/admin-guide/gpio/index.rst

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gpio-aggregator
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sysfs
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gpio-mockup
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gpio-sim
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.. only:: subproject and html
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Documentation/arm/marvell.rst

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-------------
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Flavors:
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- 88F6500
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- 88F6510
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- 88F6530P
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- 88F6550
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- 88F6560
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- 88F6601
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Homepage:
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https://web.archive.org/web/20181005145041/http://www.marvell.com/broadband/

Documentation/arm64/silicon-errata.rst

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| Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 |
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+----------------+-----------------+-----------------+-----------------------------+
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2064142 | ARM64_ERRATUM_2064142 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2038923 | ARM64_ERRATUM_2038923 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #1902691 | ARM64_ERRATUM_1902691 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2051678 | ARM64_ERRATUM_2051678 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2077057 | ARM64_ERRATUM_2077057 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #2224489 | ARM64_ERRATUM_2224489 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1188873,1418040| ARM64_ERRATUM_1418040 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Neoverse-N1 | #1349291 | N/A |

Documentation/core-api/dma-attributes.rst

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subsystem that the buffer is fully accessible at the elevated privilege
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level (and ideally inaccessible or at least read-only at the
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lesser-privileged levels).
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DMA_ATTR_OVERWRITE
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------------------
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This is a hint to the DMA-mapping subsystem that the device is expected to
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overwrite the entire mapped size, thus the caller does not require any of the
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previous buffer contents to be preserved. This allows bounce-buffering
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implementations to optimise DMA_FROM_DEVICE transfers.

Documentation/cpu-freq/cpu-drivers.rst

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.resume - A pointer to a per-policy resume function which is called
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with interrupts disabled and _before_ the governor is started again.
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.ready - A pointer to a per-policy ready function which is called after
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the policy is fully initialized.
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.attr - A pointer to a NULL-terminated list of "struct freq_attr" which
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Documentation/dev-tools/kselftest.rst

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paths in the kernel. Tests are intended to be run after building, installing
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Kselftest from mainline can be run on older stable kernels. Running tests
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from mainline offers the best coverage. Several test rings run mainline
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kselftest suite on stable releases. The reason is that when a new test
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gets added to test existing code to regression test a bug, we should be
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able to run that test on an older kernel. Hence, it is important to keep
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code that can still test an older kernel and make sure it skips the test
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gracefully on newer releases.
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You can find additional information on Kselftest framework, how to
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write new tests using the framework on Kselftest wiki:
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