We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 0653d50 commit 4a36e46Copy full SHA for 4a36e46
drivers/gpu/drm/i915/display/intel_dp.c
@@ -2725,7 +2725,11 @@ intel_dp_drrs_compute_config(struct intel_connector *connector,
2725
intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode);
2726
int pixel_clock;
2727
2728
- if (has_seamless_m_n(connector))
+ /*
2729
+ * FIXME all joined pipes share the same transcoder.
2730
+ * Need to account for that when updating M/N live.
2731
+ */
2732
+ if (has_seamless_m_n(connector) && !pipe_config->bigjoiner_pipes)
2733
pipe_config->update_m_n = true;
2734
2735
if (!can_enable_drrs(connector, pipe_config, downclock_mode)) {
0 commit comments