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aford173vinodkoul
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phy: freescale: fsl-samsung-hdmi: Replace register defines with macro
There are 47 registers defined as PHY_REG_xx were xx goes from 00 to 47. Simplify this by replacing them all with a macro which is passed the register number to return the proper register offset. Signed-off-by: Adam Ford <[email protected]> Reviewed-by: Marco Felsch <[email protected]> Reviewed-by: Frieder Schrempf <[email protected]> Tested-by: Frieder Schrempf <[email protected]> Reviewed-by: Dominique Martinet <[email protected]> Tested-by: Dominique Martinet <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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‎drivers/phy/freescale/phy-fsl-samsung-hdmi.c

Lines changed: 43 additions & 90 deletions
Original file line numberDiff line numberDiff line change
@@ -14,76 +14,29 @@
1414
#include <linux/platform_device.h>
1515
#include <linux/pm_runtime.h>
1616

17-
#define PHY_REG_00 0x00
18-
#define PHY_REG_01 0x04
19-
#define PHY_REG_02 0x08
20-
#define PHY_REG_08 0x20
21-
#define PHY_REG_09 0x24
22-
#define PHY_REG_10 0x28
23-
#define PHY_REG_11 0x2c
24-
25-
#define PHY_REG_12 0x30
26-
#define REG12_CK_DIV_MASK GENMASK(5, 4)
27-
28-
#define PHY_REG_13 0x34
29-
#define REG13_TG_CODE_LOW_MASK GENMASK(7, 0)
30-
31-
#define PHY_REG_14 0x38
32-
#define REG14_TOL_MASK GENMASK(7, 4)
33-
#define REG14_RP_CODE_MASK GENMASK(3, 1)
34-
#define REG14_TG_CODE_HIGH_MASK GENMASK(0, 0)
35-
36-
#define PHY_REG_15 0x3c
37-
#define PHY_REG_16 0x40
38-
#define PHY_REG_17 0x44
39-
#define PHY_REG_18 0x48
40-
#define PHY_REG_19 0x4c
41-
#define PHY_REG_20 0x50
42-
43-
#define PHY_REG_21 0x54
44-
#define REG21_SEL_TX_CK_INV BIT(7)
45-
#define REG21_PMS_S_MASK GENMASK(3, 0)
46-
47-
#define PHY_REG_22 0x58
48-
#define PHY_REG_23 0x5c
49-
#define PHY_REG_24 0x60
50-
#define PHY_REG_25 0x64
51-
#define PHY_REG_26 0x68
52-
#define PHY_REG_27 0x6c
53-
#define PHY_REG_28 0x70
54-
#define PHY_REG_29 0x74
55-
#define PHY_REG_30 0x78
56-
#define PHY_REG_31 0x7c
57-
#define PHY_REG_32 0x80
17+
#define PHY_REG(reg) (reg * 4)
5818

19+
#define REG12_CK_DIV_MASK GENMASK(5, 4)
20+
21+
#define REG13_TG_CODE_LOW_MASK GENMASK(7, 0)
22+
23+
#define REG14_TOL_MASK GENMASK(7, 4)
24+
#define REG14_RP_CODE_MASK GENMASK(3, 1)
25+
#define REG14_TG_CODE_HIGH_MASK GENMASK(0, 0)
26+
27+
#define REG21_SEL_TX_CK_INV BIT(7)
28+
#define REG21_PMS_S_MASK GENMASK(3, 0)
5929
/*
6030
* REG33 does not match the ref manual. According to Sandor Yu from NXP,
6131
* "There is a doc issue on the i.MX8MP latest RM"
6232
* REG33 is being used per guidance from Sandor
6333
*/
34+
#define REG33_MODE_SET_DONE BIT(7)
35+
#define REG33_FIX_DA BIT(1)
6436

65-
#define PHY_REG_33 0x84
66-
#define REG33_MODE_SET_DONE BIT(7)
67-
#define REG33_FIX_DA BIT(1)
68-
69-
#define PHY_REG_34 0x88
70-
#define REG34_PHY_READY BIT(7)
71-
#define REG34_PLL_LOCK BIT(6)
72-
#define REG34_PHY_CLK_READY BIT(5)
73-
74-
#define PHY_REG_35 0x8c
75-
#define PHY_REG_36 0x90
76-
#define PHY_REG_37 0x94
77-
#define PHY_REG_38 0x98
78-
#define PHY_REG_39 0x9c
79-
#define PHY_REG_40 0xa0
80-
#define PHY_REG_41 0xa4
81-
#define PHY_REG_42 0xa8
82-
#define PHY_REG_43 0xac
83-
#define PHY_REG_44 0xb0
84-
#define PHY_REG_45 0xb4
85-
#define PHY_REG_46 0xb8
86-
#define PHY_REG_47 0xbc
37+
#define REG34_PHY_READY BIT(7)
38+
#define REG34_PLL_LOCK BIT(6)
39+
#define REG34_PHY_CLK_READY BIT(5)
8740

8841
#define PHY_PLL_DIV_REGS_NUM 6
8942

@@ -369,29 +322,29 @@ struct reg_settings {
369322
};
370323

371324
static const struct reg_settings common_phy_cfg[] = {
372-
{ PHY_REG_00, 0x00 }, { PHY_REG_01, 0xd1 },
373-
{ PHY_REG_08, 0x4f }, { PHY_REG_09, 0x30 },
374-
{ PHY_REG_10, 0x33 }, { PHY_REG_11, 0x65 },
325+
{ PHY_REG(0), 0x00 }, { PHY_REG(1), 0xd1 },
326+
{ PHY_REG(8), 0x4f }, { PHY_REG(9), 0x30 },
327+
{ PHY_REG(10), 0x33 }, { PHY_REG(11), 0x65 },
375328
/* REG12 pixclk specific */
376329
/* REG13 pixclk specific */
377330
/* REG14 pixclk specific */
378-
{ PHY_REG_15, 0x80 }, { PHY_REG_16, 0x6c },
379-
{ PHY_REG_17, 0xf2 }, { PHY_REG_18, 0x67 },
380-
{ PHY_REG_19, 0x00 }, { PHY_REG_20, 0x10 },
331+
{ PHY_REG(15), 0x80 }, { PHY_REG(16), 0x6c },
332+
{ PHY_REG(17), 0xf2 }, { PHY_REG(18), 0x67 },
333+
{ PHY_REG(19), 0x00 }, { PHY_REG(20), 0x10 },
381334
/* REG21 pixclk specific */
382-
{ PHY_REG_22, 0x30 }, { PHY_REG_23, 0x32 },
383-
{ PHY_REG_24, 0x60 }, { PHY_REG_25, 0x8f },
384-
{ PHY_REG_26, 0x00 }, { PHY_REG_27, 0x00 },
385-
{ PHY_REG_28, 0x08 }, { PHY_REG_29, 0x00 },
386-
{ PHY_REG_30, 0x00 }, { PHY_REG_31, 0x00 },
387-
{ PHY_REG_32, 0x00 }, { PHY_REG_33, 0x80 },
388-
{ PHY_REG_34, 0x00 }, { PHY_REG_35, 0x00 },
389-
{ PHY_REG_36, 0x00 }, { PHY_REG_37, 0x00 },
390-
{ PHY_REG_38, 0x00 }, { PHY_REG_39, 0x00 },
391-
{ PHY_REG_40, 0x00 }, { PHY_REG_41, 0xe0 },
392-
{ PHY_REG_42, 0x83 }, { PHY_REG_43, 0x0f },
393-
{ PHY_REG_44, 0x3E }, { PHY_REG_45, 0xf8 },
394-
{ PHY_REG_46, 0x00 }, { PHY_REG_47, 0x00 }
335+
{ PHY_REG(22), 0x30 }, { PHY_REG(23), 0x32 },
336+
{ PHY_REG(24), 0x60 }, { PHY_REG(25), 0x8f },
337+
{ PHY_REG(26), 0x00 }, { PHY_REG(27), 0x00 },
338+
{ PHY_REG(28), 0x08 }, { PHY_REG(29), 0x00 },
339+
{ PHY_REG(30), 0x00 }, { PHY_REG(31), 0x00 },
340+
{ PHY_REG(32), 0x00 }, { PHY_REG(33), 0x80 },
341+
{ PHY_REG(34), 0x00 }, { PHY_REG(35), 0x00 },
342+
{ PHY_REG(36), 0x00 }, { PHY_REG(37), 0x00 },
343+
{ PHY_REG(38), 0x00 }, { PHY_REG(39), 0x00 },
344+
{ PHY_REG(40), 0x00 }, { PHY_REG(41), 0xe0 },
345+
{ PHY_REG(42), 0x83 }, { PHY_REG(43), 0x0f },
346+
{ PHY_REG(44), 0x3E }, { PHY_REG(45), 0xf8 },
347+
{ PHY_REG(46), 0x00 }, { PHY_REG(47), 0x00 }
395348
};
396349

397350
struct fsl_samsung_hdmi_phy {
@@ -442,7 +395,7 @@ fsl_samsung_hdmi_phy_configure_pixclk(struct fsl_samsung_hdmi_phy *phy,
442395
}
443396

444397
writeb(REG21_SEL_TX_CK_INV | FIELD_PREP(REG21_PMS_S_MASK, div),
445-
phy->regs + PHY_REG_21);
398+
phy->regs + PHY_REG(21));
446399
}
447400

448401
static void
@@ -469,7 +422,7 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy,
469422
break;
470423
}
471424

472-
writeb(FIELD_PREP(REG12_CK_DIV_MASK, ilog2(div)), phy->regs + PHY_REG_12);
425+
writeb(FIELD_PREP(REG12_CK_DIV_MASK, ilog2(div)), phy->regs + PHY_REG(12));
473426

474427
/*
475428
* Calculation for the frequency lock detector target code (fld_tg_code)
@@ -489,11 +442,11 @@ fsl_samsung_hdmi_phy_configure_pll_lock_det(struct fsl_samsung_hdmi_phy *phy,
489442

490443
/* FLD_TOL and FLD_RP_CODE taken from downstream driver */
491444
writeb(FIELD_PREP(REG13_TG_CODE_LOW_MASK, fld_tg_code),
492-
phy->regs + PHY_REG_13);
445+
phy->regs + PHY_REG(13));
493446
writeb(FIELD_PREP(REG14_TOL_MASK, 2) |
494447
FIELD_PREP(REG14_RP_CODE_MASK, 2) |
495448
FIELD_PREP(REG14_TG_CODE_HIGH_MASK, fld_tg_code >> 8),
496-
phy->regs + PHY_REG_14);
449+
phy->regs + PHY_REG(14));
497450
}
498451

499452
static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy,
@@ -503,22 +456,22 @@ static int fsl_samsung_hdmi_phy_configure(struct fsl_samsung_hdmi_phy *phy,
503456
u8 val;
504457

505458
/* HDMI PHY init */
506-
writeb(REG33_FIX_DA, phy->regs + PHY_REG_33);
459+
writeb(REG33_FIX_DA, phy->regs + PHY_REG(33));
507460

508461
/* common PHY registers */
509462
for (i = 0; i < ARRAY_SIZE(common_phy_cfg); i++)
510463
writeb(common_phy_cfg[i].val, phy->regs + common_phy_cfg[i].reg);
511464

512465
/* set individual PLL registers PHY_REG2 ... PHY_REG7 */
513466
for (i = 0; i < PHY_PLL_DIV_REGS_NUM; i++)
514-
writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG_02 + i * 4);
467+
writeb(cfg->pll_div_regs[i], phy->regs + PHY_REG(2) + i * 4);
515468

516469
fsl_samsung_hdmi_phy_configure_pixclk(phy, cfg);
517470
fsl_samsung_hdmi_phy_configure_pll_lock_det(phy, cfg);
518471

519-
writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG_33);
472+
writeb(REG33_FIX_DA | REG33_MODE_SET_DONE, phy->regs + PHY_REG(33));
520473

521-
ret = readb_poll_timeout(phy->regs + PHY_REG_34, val,
474+
ret = readb_poll_timeout(phy->regs + PHY_REG(34), val,
522475
val & REG34_PLL_LOCK, 50, 20000);
523476
if (ret)
524477
dev_err(phy->dev, "PLL failed to lock\n");

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