Skip to content

Commit 4ad7b39

Browse files
MoudyHomchehab
MoudyHo
authored and
mchehab
committed
media: dt-binding: mediatek: add bindings for MediaTek MDP3 components
This patch adds DT binding documents for Media Data Path 3 (MDP3) a unit in multimedia system combined with several components and used for scaling and color format convert. Signed-off-by: Moudy Ho <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Signed-off-by: Hans Verkuil <[email protected]> Signed-off-by: Mauro Carvalho Chehab <[email protected]>
1 parent 1c78f19 commit 4ad7b39

File tree

3 files changed

+252
-0
lines changed

3 files changed

+252
-0
lines changed

‎Documentation/devicetree/bindings/media/mediatek,mdp3-rdma.yaml

Lines changed: 95 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,95 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: MediaTek Read Direct Memory Access
8+
9+
maintainers:
10+
- Matthias Brugger <[email protected]>
11+
- Moudy Ho <[email protected]>
12+
13+
description: |
14+
MediaTek Read Direct Memory Access(RDMA) component used to do read DMA.
15+
It contains one line buffer to store the sufficient pixel data, and
16+
must be siblings to the central MMSYS_CONFIG node.
17+
For a description of the MMSYS_CONFIG binding, see
18+
Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
19+
for details.
20+
21+
properties:
22+
compatible:
23+
items:
24+
- const: mediatek,mt8183-mdp3-rdma
25+
26+
reg:
27+
maxItems: 1
28+
29+
mediatek,gce-client-reg:
30+
$ref: '/schemas/types.yaml#/definitions/phandle-array'
31+
items:
32+
items:
33+
- description: phandle of GCE
34+
- description: GCE subsys id
35+
- description: register offset
36+
- description: register size
37+
description: The register of client driver can be configured by gce with
38+
4 arguments defined in this property. Each GCE subsys id is mapping to
39+
a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
40+
41+
mediatek,gce-events:
42+
description:
43+
The event id which is mapping to the specific hardware event signal
44+
to gce. The event id is defined in the gce header
45+
include/dt-bindings/gce/<chip>-gce.h of each chips.
46+
$ref: /schemas/types.yaml#/definitions/uint32-array
47+
48+
power-domains:
49+
maxItems: 1
50+
51+
clocks:
52+
items:
53+
- description: RDMA clock
54+
- description: RSZ clock
55+
56+
iommus:
57+
maxItems: 1
58+
59+
mboxes:
60+
items:
61+
- description: used for 1st data pipe from RDMA
62+
- description: used for 2nd data pipe from RDMA
63+
64+
required:
65+
- compatible
66+
- reg
67+
- mediatek,gce-client-reg
68+
- mediatek,gce-events
69+
- power-domains
70+
- clocks
71+
- iommus
72+
- mboxes
73+
74+
additionalProperties: false
75+
76+
examples:
77+
- |
78+
#include <dt-bindings/clock/mt8183-clk.h>
79+
#include <dt-bindings/gce/mt8183-gce.h>
80+
#include <dt-bindings/power/mt8183-power.h>
81+
#include <dt-bindings/memory/mt8183-larb-port.h>
82+
83+
mdp3_rdma0: mdp3-rdma0@14001000 {
84+
compatible = "mediatek,mt8183-mdp3-rdma";
85+
reg = <0x14001000 0x1000>;
86+
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>;
87+
mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>,
88+
<CMDQ_EVENT_MDP_RDMA0_EOF>;
89+
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
90+
clocks = <&mmsys CLK_MM_MDP_RDMA0>,
91+
<&mmsys CLK_MM_MDP_RSZ1>;
92+
iommus = <&iommu>;
93+
mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST>,
94+
<&gce 21 CMDQ_THR_PRIO_LOWEST>;
95+
};

‎Documentation/devicetree/bindings/media/mediatek,mdp3-rsz.yaml

Lines changed: 77 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,77 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/media/mediatek,mdp3-rsz.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: MediaTek Resizer
8+
9+
maintainers:
10+
- Matthias Brugger <[email protected]>
11+
- Moudy Ho <[email protected]>
12+
13+
description: |
14+
One of Media Data Path 3 (MDP3) components used to do frame resizing.
15+
16+
properties:
17+
compatible:
18+
items:
19+
- enum:
20+
- mediatek,mt8183-mdp3-rsz
21+
22+
reg:
23+
maxItems: 1
24+
25+
mediatek,gce-client-reg:
26+
$ref: /schemas/types.yaml#/definitions/phandle-array
27+
items:
28+
items:
29+
- description: phandle of GCE
30+
- description: GCE subsys id
31+
- description: register offset
32+
- description: register size
33+
description: The register of client driver can be configured by gce with
34+
4 arguments defined in this property. Each GCE subsys id is mapping to
35+
a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
36+
37+
mediatek,gce-events:
38+
description:
39+
The event id which is mapping to the specific hardware event signal
40+
to gce. The event id is defined in the gce header
41+
include/dt-bindings/gce/<chip>-gce.h of each chips.
42+
$ref: /schemas/types.yaml#/definitions/uint32-array
43+
44+
clocks:
45+
minItems: 1
46+
47+
required:
48+
- compatible
49+
- reg
50+
- mediatek,gce-client-reg
51+
- mediatek,gce-events
52+
- clocks
53+
54+
additionalProperties: false
55+
56+
examples:
57+
- |
58+
#include <dt-bindings/clock/mt8183-clk.h>
59+
#include <dt-bindings/gce/mt8183-gce.h>
60+
61+
mdp3_rsz0: mdp3-rsz0@14003000 {
62+
compatible = "mediatek,mt8183-mdp3-rsz";
63+
reg = <0x14003000 0x1000>;
64+
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>;
65+
mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ0_SOF>,
66+
<CMDQ_EVENT_MDP_RSZ0_EOF>;
67+
clocks = <&mmsys CLK_MM_MDP_RSZ0>;
68+
};
69+
70+
mdp3_rsz1: mdp3-rsz1@14004000 {
71+
compatible = "mediatek,mt8183-mdp3-rsz";
72+
reg = <0x14004000 0x1000>;
73+
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>;
74+
mediatek,gce-events = <CMDQ_EVENT_MDP_RSZ1_SOF>,
75+
<CMDQ_EVENT_MDP_RSZ1_EOF>;
76+
clocks = <&mmsys CLK_MM_MDP_RSZ1>;
77+
};

‎Documentation/devicetree/bindings/media/mediatek,mdp3-wrot.yaml

Lines changed: 80 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,80 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/media/mediatek,mdp3-wrot.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: MediaTek Write DMA with Rotation
8+
9+
maintainers:
10+
- Matthias Brugger <[email protected]>
11+
- Moudy Ho <[email protected]>
12+
13+
description: |
14+
One of Media Data Path 3 (MDP3) components used to write DMA with frame rotation.
15+
16+
properties:
17+
compatible:
18+
items:
19+
- enum:
20+
- mediatek,mt8183-mdp3-wrot
21+
22+
reg:
23+
maxItems: 1
24+
25+
mediatek,gce-client-reg:
26+
$ref: /schemas/types.yaml#/definitions/phandle-array
27+
items:
28+
items:
29+
- description: phandle of GCE
30+
- description: GCE subsys id
31+
- description: register offset
32+
- description: register size
33+
description: The register of client driver can be configured by gce with
34+
4 arguments defined in this property. Each GCE subsys id is mapping to
35+
a client defined in the header include/dt-bindings/gce/<chip>-gce.h.
36+
37+
mediatek,gce-events:
38+
description:
39+
The event id which is mapping to the specific hardware event signal
40+
to gce. The event id is defined in the gce header
41+
include/dt-bindings/gce/<chip>-gce.h of each chips.
42+
$ref: /schemas/types.yaml#/definitions/uint32-array
43+
44+
power-domains:
45+
maxItems: 1
46+
47+
clocks:
48+
minItems: 1
49+
50+
iommus:
51+
maxItems: 1
52+
53+
required:
54+
- compatible
55+
- reg
56+
- mediatek,gce-client-reg
57+
- mediatek,gce-events
58+
- power-domains
59+
- clocks
60+
- iommus
61+
62+
additionalProperties: false
63+
64+
examples:
65+
- |
66+
#include <dt-bindings/clock/mt8183-clk.h>
67+
#include <dt-bindings/gce/mt8183-gce.h>
68+
#include <dt-bindings/power/mt8183-power.h>
69+
#include <dt-bindings/memory/mt8183-larb-port.h>
70+
71+
mdp3_wrot0: mdp3-wrot0@14005000 {
72+
compatible = "mediatek,mt8183-mdp3-wrot";
73+
reg = <0x14005000 0x1000>;
74+
mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
75+
mediatek,gce-events = <CMDQ_EVENT_MDP_WROT0_SOF>,
76+
<CMDQ_EVENT_MDP_WROT0_EOF>;
77+
power-domains = <&spm MT8183_POWER_DOMAIN_DISP>;
78+
clocks = <&mmsys CLK_MM_MDP_WROT0>;
79+
iommus = <&iommu>;
80+
};

0 commit comments

Comments
 (0)