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ARM: mv78xx0: add code to enable XOR and CRYPTO engines on mv78xx0
Adding missing code/values required to enable the XOR and CESA engines for this SoC Signed-off-by: Jeremy J. Peper <[email protected]> Signed-off-by: Arnd Bergmann <[email protected]>
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arch/arm/mach-mv78xx0/buffalo-wxl-setup.c

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@@ -119,6 +119,8 @@ static void __init wxl_init(void)
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mv78xx0_uart1_init();
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mv78xx0_uart2_init();
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mv78xx0_uart3_init();
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mv78xx0_xor_init();
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mv78xx0_crypto_init();
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mv78xx0_i2c_init();
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i2c_register_board_info(0, &db78x00_i2c_rtc, 1);
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}

arch/arm/mach-mv78xx0/common.c

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@@ -342,6 +342,29 @@ void __ref mv78xx0_timer_init(void)
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IRQ_MV78XX0_TIMER_1, get_tclk());
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}
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/****************************************************************************
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* XOR engine
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****************************************************************************/
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void __init mv78xx0_xor_init(void)
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{
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orion_xor0_init(XOR_PHYS_BASE,
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XOR_PHYS_BASE + 0x200,
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IRQ_MV78XX0_XOR_0, IRQ_MV78XX0_XOR_1);
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}
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/****************************************************************************
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* Cryptographic Engines and Security Accelerator (CESA)
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****************************************************************************/
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void __init mv78xx0_crypto_init(void)
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{
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mvebu_mbus_add_window_by_id(MV78XX0_MBUS_SRAM_TARGET,
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MV78XX0_MBUS_SRAM_ATTR,
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MV78XX0_SRAM_PHYS_BASE,
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MV78XX0_SRAM_SIZE);
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orion_crypto_init(CRYPTO_PHYS_BASE, MV78XX0_SRAM_PHYS_BASE,
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SZ_8K, IRQ_MV78XX0_CRYPTO);
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}
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/*****************************************************************************
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* General

arch/arm/mach-mv78xx0/common.h

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@@ -43,6 +43,8 @@ void mv78xx0_uart0_init(void);
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void mv78xx0_uart1_init(void);
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void mv78xx0_uart2_init(void);
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void mv78xx0_uart3_init(void);
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void mv78xx0_xor_init(void);
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void mv78xx0_crypto_init(void);
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void mv78xx0_i2c_init(void);
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void mv78xx0_restart(enum reboot_mode, const char *);
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arch/arm/mach-mv78xx0/mv78xx0.h

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@@ -49,9 +49,15 @@
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#define MV78XX0_REGS_VIRT_BASE IOMEM(0xfec00000)
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#define MV78XX0_REGS_SIZE SZ_1M
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#define MV78XX0_SRAM_PHYS_BASE (0xf2200000)
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#define MV78XX0_SRAM_SIZE SZ_8K
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#define MV78XX0_PCIE_MEM_PHYS_BASE 0xc0000000
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#define MV78XX0_PCIE_MEM_SIZE 0x30000000
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#define MV78XX0_MBUS_SRAM_TARGET 0x09
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#define MV78XX0_MBUS_SRAM_ATTR 0x00
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/*
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* Core-specific peripheral registers.
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*/
@@ -98,6 +104,8 @@
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#define USB1_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x51000)
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#define USB2_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x52000)
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#define XOR_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x60900)
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#define GE00_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x70000)
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#define GE01_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x74000)
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@@ -106,6 +114,8 @@
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#define PCIE12_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x88000)
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#define PCIE13_VIRT_BASE (MV78XX0_REGS_VIRT_BASE + 0x8c000)
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#define CRYPTO_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0x90000)
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#define SATA_PHYS_BASE (MV78XX0_REGS_PHYS_BASE + 0xa0000)
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/*

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