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SamShih33
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clk: mediatek: add drivers for MT7988 SoC
Add APMIXED, ETH, INFRACFG and TOPCKGEN clock drivers which are typical MediaTek designs. Also add driver for XFIPLL clock generating the 156.25MHz clock for the XFI SerDes. It needs an undocumented software workaround and has an unknown internal design. Signed-off-by: Sam Shih <[email protected]> Signed-off-by: Daniel Golle <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/c7574d808e2da1a530182f0fd790c1337c336e1b.1702849494.git.daniel@makrotopia.org [[email protected]: Add module license to infracfg file] Signed-off-by: Stephen Boyd <[email protected]>
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‎drivers/clk/mediatek/Kconfig

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@@ -423,6 +423,15 @@ config COMMON_CLK_MT7986_ETHSYS
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This driver adds support for clocks for Ethernet and SGMII
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required on MediaTek MT7986 SoC.
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426+
config COMMON_CLK_MT7988
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tristate "Clock driver for MediaTek MT7988"
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depends on ARCH_MEDIATEK || COMPILE_TEST
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select COMMON_CLK_MEDIATEK
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default ARCH_MEDIATEK
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help
432+
This driver supports MediaTek MT7988 basic clocks and clocks
433+
required for various periperals found on this SoC.
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426435
config COMMON_CLK_MT8135
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tristate "Clock driver for MediaTek MT8135"
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depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST

‎drivers/clk/mediatek/Makefile

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@@ -62,6 +62,11 @@ obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-apmixed.o
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obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-topckgen.o
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obj-$(CONFIG_COMMON_CLK_MT7986) += clk-mt7986-infracfg.o
6464
obj-$(CONFIG_COMMON_CLK_MT7986_ETHSYS) += clk-mt7986-eth.o
65+
obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-apmixed.o
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obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-topckgen.o
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obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-infracfg.o
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obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-eth.o
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obj-$(CONFIG_COMMON_CLK_MT7988) += clk-mt7988-xfipll.o
6570
obj-$(CONFIG_COMMON_CLK_MT8135) += clk-mt8135-apmixedsys.o clk-mt8135.o
6671
obj-$(CONFIG_COMMON_CLK_MT8167) += clk-mt8167-apmixedsys.o clk-mt8167.o
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obj-$(CONFIG_COMMON_CLK_MT8167_AUDSYS) += clk-mt8167-aud.o

‎drivers/clk/mediatek/clk-mt7988-apmixed.c

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@@ -0,0 +1,114 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2023 MediaTek Inc.
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* Author: Sam Shih <[email protected]>
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* Author: Xiufeng Li <[email protected]>
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*/
7+
8+
#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include "clk-mux.h"
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#include "clk-pll.h"
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#include <dt-bindings/clock/mediatek,mt7988-clk.h>
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#define MT7988_PLL_FMAX (2500UL * MHZ)
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#define MT7988_PCW_CHG_BIT 2
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#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _rst_bar_mask, _pcwbits, _pd_reg, \
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_pd_shift, _tuner_reg, _tuner_en_reg, _tuner_en_bit, _pcw_reg, _pcw_shift, \
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_pcw_chg_reg) \
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{ \
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.id = _id, \
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.name = _name, \
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.reg = _reg, \
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.pwr_reg = _pwr_reg, \
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.en_mask = _en_mask, \
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.flags = _flags, \
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.rst_bar_mask = BIT(_rst_bar_mask), \
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.fmax = MT7988_PLL_FMAX, \
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.pcwbits = _pcwbits, \
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.pd_reg = _pd_reg, \
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.pd_shift = _pd_shift, \
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.tuner_reg = _tuner_reg, \
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.tuner_en_reg = _tuner_en_reg, \
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.tuner_en_bit = _tuner_en_bit, \
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.pcw_reg = _pcw_reg, \
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.pcw_shift = _pcw_shift, \
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.pcw_chg_reg = _pcw_chg_reg, \
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.pcw_chg_bit = MT7988_PCW_CHG_BIT, \
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.parent_name = "clkxtal", \
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}
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static const struct mtk_pll_data plls[] = {
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PLL(CLK_APMIXED_NETSYSPLL, "netsyspll", 0x0104, 0x0110, 0x00000001, 0, 0, 32, 0x0104, 4, 0,
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0, 0, 0x0108, 0, 0x0104),
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PLL(CLK_APMIXED_MPLL, "mpll", 0x0114, 0x0120, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0114, 4,
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0, 0, 0, 0x0118, 0, 0x0114),
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PLL(CLK_APMIXED_MMPLL, "mmpll", 0x0124, 0x0130, 0xff000001, HAVE_RST_BAR, 23, 32, 0x0124, 4,
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0, 0, 0, 0x0128, 0, 0x0124),
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PLL(CLK_APMIXED_APLL2, "apll2", 0x0134, 0x0140, 0x00000001, 0, 0, 32, 0x0134, 4, 0x0704,
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0x0700, 1, 0x0138, 0, 0x0134),
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PLL(CLK_APMIXED_NET1PLL, "net1pll", 0x0144, 0x0150, 0xff000001, HAVE_RST_BAR, 23, 32,
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0x0144, 4, 0, 0, 0, 0x0148, 0, 0x0144),
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PLL(CLK_APMIXED_NET2PLL, "net2pll", 0x0154, 0x0160, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23,
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32, 0x0154, 4, 0, 0, 0, 0x0158, 0, 0x0154),
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PLL(CLK_APMIXED_WEDMCUPLL, "wedmcupll", 0x0164, 0x0170, 0x00000001, 0, 0, 32, 0x0164, 4, 0,
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0, 0, 0x0168, 0, 0x0164),
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PLL(CLK_APMIXED_SGMPLL, "sgmpll", 0x0174, 0x0180, 0x00000001, 0, 0, 32, 0x0174, 4, 0, 0, 0,
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0x0178, 0, 0x0174),
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PLL(CLK_APMIXED_ARM_B, "arm_b", 0x0204, 0x0210, 0xff000001, (HAVE_RST_BAR | PLL_AO), 23, 32,
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0x0204, 4, 0, 0, 0, 0x0208, 0, 0x0204),
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PLL(CLK_APMIXED_CCIPLL2_B, "ccipll2_b", 0x0214, 0x0220, 0xff000001, HAVE_RST_BAR, 23, 32,
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0x0214, 4, 0, 0, 0, 0x0218, 0, 0x0214),
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PLL(CLK_APMIXED_USXGMIIPLL, "usxgmiipll", 0x0304, 0x0310, 0xff000001, HAVE_RST_BAR, 23, 32,
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0x0304, 4, 0, 0, 0, 0x0308, 0, 0x0304),
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PLL(CLK_APMIXED_MSDCPLL, "msdcpll", 0x0314, 0x0320, 0x00000001, 0, 0, 32, 0x0314, 4, 0, 0,
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0, 0x0318, 0, 0x0314),
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};
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static const struct of_device_id of_match_clk_mt7988_apmixed[] = {
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{ .compatible = "mediatek,mt7988-apmixedsys" },
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{ /* sentinel */ }
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};
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static int clk_mt7988_apmixed_probe(struct platform_device *pdev)
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{
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struct clk_hw_onecell_data *clk_data;
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struct device_node *node = pdev->dev.of_node;
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int r;
84+
85+
clk_data = mtk_alloc_clk_data(ARRAY_SIZE(plls));
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if (!clk_data)
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return -ENOMEM;
88+
89+
r = mtk_clk_register_plls(node, plls, ARRAY_SIZE(plls), clk_data);
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if (r)
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goto free_apmixed_data;
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r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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if (r)
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goto unregister_plls;
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return r;
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unregister_plls:
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mtk_clk_unregister_plls(plls, ARRAY_SIZE(plls), clk_data);
101+
free_apmixed_data:
102+
mtk_free_clk_data(clk_data);
103+
return r;
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}
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static struct platform_driver clk_mt7988_apmixed_drv = {
107+
.probe = clk_mt7988_apmixed_probe,
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.driver = {
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.name = "clk-mt7988-apmixed",
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.of_match_table = of_match_clk_mt7988_apmixed,
111+
},
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};
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builtin_platform_driver(clk_mt7988_apmixed_drv);
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MODULE_LICENSE("GPL");

‎drivers/clk/mediatek/clk-mt7988-eth.c

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@@ -0,0 +1,150 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
3+
* Copyright (c) 2023 MediaTek Inc.
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* Author: Sam Shih <[email protected]>
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* Author: Xiufeng Li <[email protected]>
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*/
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8+
#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include "clk-mtk.h"
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#include "clk-gate.h"
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#include "reset.h"
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#include <dt-bindings/clock/mediatek,mt7988-clk.h>
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#include <dt-bindings/reset/mediatek,mt7988-resets.h>
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static const struct mtk_gate_regs ethdma_cg_regs = {
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.set_ofs = 0x30,
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.clr_ofs = 0x30,
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.sta_ofs = 0x30,
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};
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#define GATE_ETHDMA(_id, _name, _parent, _shift) \
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{ \
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.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &ethdma_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr_inv, \
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}
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static const struct mtk_gate ethdma_clks[] = {
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GATE_ETHDMA(CLK_ETHDMA_XGP1_EN, "ethdma_xgp1_en", "top_xtal", 0),
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GATE_ETHDMA(CLK_ETHDMA_XGP2_EN, "ethdma_xgp2_en", "top_xtal", 1),
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GATE_ETHDMA(CLK_ETHDMA_XGP3_EN, "ethdma_xgp3_en", "top_xtal", 2),
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GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", "netsys_2x_sel", 6),
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GATE_ETHDMA(CLK_ETHDMA_GP2_EN, "ethdma_gp2_en", "top_xtal", 7),
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GATE_ETHDMA(CLK_ETHDMA_GP1_EN, "ethdma_gp1_en", "top_xtal", 8),
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GATE_ETHDMA(CLK_ETHDMA_GP3_EN, "ethdma_gp3_en", "top_xtal", 10),
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GATE_ETHDMA(CLK_ETHDMA_ESW_EN, "ethdma_esw_en", "netsys_gsw_sel", 16),
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GATE_ETHDMA(CLK_ETHDMA_CRYPT0_EN, "ethdma_crypt0_en", "eip197_sel", 29),
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};
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static const struct mtk_clk_desc ethdma_desc = {
48+
.clks = ethdma_clks,
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.num_clks = ARRAY_SIZE(ethdma_clks),
50+
};
51+
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static const struct mtk_gate_regs sgmii_cg_regs = {
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.set_ofs = 0xe4,
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.clr_ofs = 0xe4,
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.sta_ofs = 0xe4,
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};
57+
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#define GATE_SGMII(_id, _name, _parent, _shift) \
59+
{ \
60+
.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
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.regs = &sgmii_cg_regs, \
64+
.shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr_inv, \
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}
67+
68+
static const struct mtk_gate sgmii0_clks[] = {
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GATE_SGMII(CLK_SGM0_TX_EN, "sgm0_tx_en", "top_xtal", 2),
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GATE_SGMII(CLK_SGM0_RX_EN, "sgm0_rx_en", "top_xtal", 3),
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};
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static const struct mtk_clk_desc sgmii0_desc = {
74+
.clks = sgmii0_clks,
75+
.num_clks = ARRAY_SIZE(sgmii0_clks),
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};
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static const struct mtk_gate sgmii1_clks[] = {
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GATE_SGMII(CLK_SGM1_TX_EN, "sgm1_tx_en", "top_xtal", 2),
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GATE_SGMII(CLK_SGM1_RX_EN, "sgm1_rx_en", "top_xtal", 3),
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};
82+
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static const struct mtk_clk_desc sgmii1_desc = {
84+
.clks = sgmii1_clks,
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.num_clks = ARRAY_SIZE(sgmii1_clks),
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};
87+
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static const struct mtk_gate_regs ethwarp_cg_regs = {
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.set_ofs = 0x14,
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.clr_ofs = 0x14,
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.sta_ofs = 0x14,
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};
93+
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#define GATE_ETHWARP(_id, _name, _parent, _shift) \
95+
{ \
96+
.id = _id, \
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.name = _name, \
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.parent_name = _parent, \
99+
.regs = &ethwarp_cg_regs, \
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.shift = _shift, \
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.ops = &mtk_clk_gate_ops_no_setclr_inv, \
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}
103+
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static const struct mtk_gate ethwarp_clks[] = {
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GATE_ETHWARP(CLK_ETHWARP_WOCPU2_EN, "ethwarp_wocpu2_en", "netsys_mcu_sel", 13),
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GATE_ETHWARP(CLK_ETHWARP_WOCPU1_EN, "ethwarp_wocpu1_en", "netsys_mcu_sel", 14),
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GATE_ETHWARP(CLK_ETHWARP_WOCPU0_EN, "ethwarp_wocpu0_en", "netsys_mcu_sel", 15),
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};
109+
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static u16 ethwarp_rst_ofs[] = { 0x8 };
111+
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static u16 ethwarp_idx_map[] = {
113+
[MT7988_ETHWARP_RST_SWITCH] = 9,
114+
};
115+
116+
static const struct mtk_clk_rst_desc ethwarp_rst_desc = {
117+
.version = MTK_RST_SIMPLE,
118+
.rst_bank_ofs = ethwarp_rst_ofs,
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.rst_bank_nr = ARRAY_SIZE(ethwarp_rst_ofs),
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.rst_idx_map = ethwarp_idx_map,
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.rst_idx_map_nr = ARRAY_SIZE(ethwarp_idx_map),
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};
123+
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static const struct mtk_clk_desc ethwarp_desc = {
125+
.clks = ethwarp_clks,
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.num_clks = ARRAY_SIZE(ethwarp_clks),
127+
.rst_desc = &ethwarp_rst_desc,
128+
};
129+
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static const struct of_device_id of_match_clk_mt7988_eth[] = {
131+
{ .compatible = "mediatek,mt7988-ethsys", .data = &ethdma_desc },
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{ .compatible = "mediatek,mt7988-sgmiisys0", .data = &sgmii0_desc },
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{ .compatible = "mediatek,mt7988-sgmiisys1", .data = &sgmii1_desc },
134+
{ .compatible = "mediatek,mt7988-ethwarp", .data = &ethwarp_desc },
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, of_match_clk_mt7988_eth);
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static struct platform_driver clk_mt7988_eth_drv = {
140+
.driver = {
141+
.name = "clk-mt7988-eth",
142+
.of_match_table = of_match_clk_mt7988_eth,
143+
},
144+
.probe = mtk_clk_simple_probe,
145+
.remove_new = mtk_clk_simple_remove,
146+
};
147+
module_platform_driver(clk_mt7988_eth_drv);
148+
149+
MODULE_DESCRIPTION("MediaTek MT7988 Ethernet clocks driver");
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MODULE_LICENSE("GPL");

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