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Ben Skeggs
committed
drm/nouveau/acr/ga102: initial support
v2. fixup for ga103 early merge Signed-off-by: Ben Skeggs <[email protected]> Signed-off-by: Gourav Samaiya <[email protected]>
1 parent a51c69e commit 4b569de

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28 files changed

+1091
-14
lines changed

28 files changed

+1091
-14
lines changed

‎drivers/gpu/drm/nouveau/include/nvfw/acr.h

Lines changed: 85 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -39,6 +39,23 @@ struct wpr_header_v1 {
3939

4040
void wpr_header_v1_dump(struct nvkm_subdev *, const struct wpr_header_v1 *);
4141

42+
struct wpr_generic_header {
43+
#define WPR_GENERIC_HEADER_ID_LSF_UCODE_DESC 1
44+
#define WPR_GENERIC_HEADER_ID_LSF_WPR_HEADER 2
45+
#define WPR_GENERIC_HEADER_ID_LSF_SHARED_SUB_WPR 3
46+
#define WPR_GENERIC_HEADER_ID_LSF_LSB_HEADER 4
47+
u16 identifier;
48+
u16 version;
49+
u32 size;
50+
};
51+
52+
struct wpr_header_v2 {
53+
struct wpr_generic_header hdr;
54+
struct wpr_header_v1 wpr;
55+
};
56+
57+
void wpr_header_v2_dump(struct nvkm_subdev *, const struct wpr_header_v2 *);
58+
4259
struct lsf_signature {
4360
u8 prd_keys[2][16];
4461
u8 dbg_keys[2][16];
@@ -89,6 +106,74 @@ struct lsb_header_v1 {
89106

90107
void lsb_header_v1_dump(struct nvkm_subdev *, struct lsb_header_v1 *);
91108

109+
struct lsb_header_v2 {
110+
struct wpr_generic_header hdr;
111+
struct lsf_signature_v2 {
112+
struct wpr_generic_header hdr;
113+
u32 falcon_id;
114+
u8 prd_present;
115+
u8 dbg_present;
116+
u16 reserved;
117+
u32 sig_size;
118+
u8 prod_sig[2][384 + 128];
119+
u8 debug_sig[2][384 + 128];
120+
u16 sig_algo_ver;
121+
u16 sig_algo;
122+
u16 hash_algo_ver;
123+
u16 hash_algo;
124+
u32 sig_algo_padding_type;
125+
u8 depmap[11 * 2 * 4];
126+
u32 depmap_count;
127+
u8 supports_versioning;
128+
u8 pad[3];
129+
u32 ls_ucode_version;
130+
u32 ls_ucode_id;
131+
u32 ucode_ls_encrypted;
132+
u32 ls_eng_algo_type;
133+
u32 ls_eng_algo_ver;
134+
u8 ls_enc_iv[16];
135+
u8 rsvd[36];
136+
} signature;
137+
u32 ucode_off;
138+
u32 ucode_size;
139+
u32 data_size;
140+
u32 bl_code_size;
141+
u32 bl_imem_off;
142+
u32 bl_data_off;
143+
u32 bl_data_size;
144+
u32 rsvd0;
145+
u32 app_code_off;
146+
u32 app_code_size;
147+
u32 app_data_off;
148+
u32 app_data_size;
149+
u32 app_imem_offset;
150+
u32 app_dmem_offset;
151+
u32 flags;
152+
u32 monitor_code_offset;
153+
u32 monitor_data_offset;
154+
u32 manifest_offset;
155+
struct hs_fmc_params {
156+
u8 hs_fmc;
157+
u8 padding[3];
158+
u16 pkc_algo;
159+
u16 pkc_algo_version;
160+
u32 engid_mask;
161+
u32 ucode_id;
162+
u32 fuse_ver;
163+
u8 pkc_signature[384 + 128];
164+
u8 pkc_key[2048];
165+
u8 rsvd[4];
166+
} hs_fmc_params;
167+
struct hs_ovl_sig_blob_params {
168+
u8 hs_ovl_sig_blob_present;
169+
u32 hs_ovl_sig_blob_offset;
170+
u32 hs_ovl_sig_blob_size;
171+
} hs_ovl_sig_blob_params;
172+
u8 rsvd[20];
173+
};
174+
175+
void lsb_header_v2_dump(struct nvkm_subdev *, struct lsb_header_v2 *);
176+
92177
struct flcn_acr_desc {
93178
union {
94179
u8 reserved_dmem[0x200];

‎drivers/gpu/drm/nouveau/include/nvfw/ls.h

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -50,4 +50,55 @@ struct nvfw_ls_desc_v1 {
5050

5151
const struct nvfw_ls_desc_v1 *
5252
nvfw_ls_desc_v1(struct nvkm_subdev *, const void *);
53+
54+
struct nvfw_ls_desc_v2 {
55+
u32 descriptor_size;
56+
u32 image_size;
57+
u32 tools_version;
58+
u32 app_version;
59+
char date[64];
60+
u32 secure_bootloader;
61+
u32 bootloader_start_offset;
62+
u32 bootloader_size;
63+
u32 bootloader_imem_offset;
64+
u32 bootloader_entry_point;
65+
u32 app_start_offset;
66+
u32 app_size;
67+
u32 app_imem_offset;
68+
u32 app_imem_entry;
69+
u32 app_dmem_offset;
70+
u32 app_resident_code_offset;
71+
u32 app_resident_code_size;
72+
u32 app_resident_data_offset;
73+
u32 app_resident_data_size;
74+
u32 nb_imem_overlays;
75+
u32 nb_dmem_overlays;
76+
struct {
77+
u32 start;
78+
u32 size;
79+
} load_ovl[64];
80+
};
81+
82+
const struct nvfw_ls_desc_v2 *nvfw_ls_desc_v2(struct nvkm_subdev *, const void *);
83+
84+
struct nvfw_ls_hsbl_bin_hdr {
85+
u32 bin_magic;
86+
u32 bin_ver;
87+
u32 bin_size;
88+
u32 header_offset;
89+
};
90+
91+
const struct nvfw_ls_hsbl_bin_hdr *nvfw_ls_hsbl_bin_hdr(struct nvkm_subdev *, const void *);
92+
93+
struct nvfw_ls_hsbl_hdr {
94+
u32 sig_prod_offset;
95+
u32 sig_prod_size;
96+
u32 patch_loc;
97+
u32 patch_sig;
98+
u32 meta_data_offset;
99+
u32 meta_data_size;
100+
u32 num_sig;
101+
};
102+
103+
const struct nvfw_ls_hsbl_hdr *nvfw_ls_hsbl_hdr(struct nvkm_subdev *, const void *);
53104
#endif

‎drivers/gpu/drm/nouveau/include/nvfw/sec2.h

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,29 @@ struct nv_sec2_init_msg {
3434
u16 sw_managed_area_size;
3535
};
3636

37+
struct nv_sec2_init_msg_v1 {
38+
struct nvfw_falcon_msg hdr;
39+
#define NV_SEC2_INIT_MSG_INIT 0x00
40+
u8 msg_type;
41+
42+
u8 num_queues;
43+
u16 os_debug_entry_point;
44+
45+
struct {
46+
u32 offset;
47+
u16 size;
48+
u8 index;
49+
#define NV_SEC2_INIT_MSG_QUEUE_ID_CMDQ 0x00
50+
#define NV_SEC2_INIT_MSG_QUEUE_ID_MSGQ 0x01
51+
u8 id;
52+
} queue_info[2];
53+
54+
u32 sw_managed_area_offset;
55+
u16 sw_managed_area_size;
56+
57+
u32 unkn[8];
58+
};
59+
3760
struct nv_sec2_acr_cmd {
3861
struct nvfw_falcon_cmd hdr;
3962
#define NV_SEC2_ACR_CMD_BOOTSTRAP_FALCON 0x00
@@ -62,4 +85,21 @@ struct nv_sec2_acr_bootstrap_falcon_msg {
6285
#define NV_SEC2_UNIT_V2_INIT 0x01
6386
#define NV_SEC2_UNIT_V2_UNLOAD 0x05
6487
#define NV_SEC2_UNIT_V2_ACR 0x07
88+
89+
struct nv_sec2_acr_bootstrap_falcon_cmd_v1 {
90+
struct nv_sec2_acr_cmd cmd;
91+
#define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_YES 0x00000000
92+
#define NV_SEC2_ACR_BOOTSTRAP_FALCON_FLAGS_RESET_NO 0x00000001
93+
u32 flags;
94+
u32 falcon_id;
95+
u32 unkn08;
96+
u32 unkn0c;
97+
};
98+
99+
struct nv_sec2_acr_bootstrap_falcon_msg_v1 {
100+
struct nv_sec2_acr_msg msg;
101+
u32 error_code;
102+
u32 falcon_id;
103+
u32 unkn08;
104+
};
65105
#endif

‎drivers/gpu/drm/nouveau/include/nvkm/core/falcon.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,7 @@ void gm200_flcn_tracepc(struct nvkm_falcon *);
6161
int gp102_flcn_reset_eng(struct nvkm_falcon *);
6262
extern const struct nvkm_falcon_func_pio gp102_flcn_emem_pio;
6363

64+
int ga102_flcn_select(struct nvkm_falcon *);
6465
int ga102_flcn_reset_prep(struct nvkm_falcon *);
6566
int ga102_flcn_reset_wait_mem_scrubbing(struct nvkm_falcon *);
6667
extern const struct nvkm_falcon_func_dma ga102_flcn_dma;

‎drivers/gpu/drm/nouveau/include/nvkm/engine/falcon.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -60,6 +60,7 @@ int nvkm_falcon_new_(const struct nvkm_falcon_func *, struct nvkm_device *,
6060
struct nvkm_falcon_func {
6161
int (*disable)(struct nvkm_falcon *);
6262
int (*enable)(struct nvkm_falcon *);
63+
int (*select)(struct nvkm_falcon *);
6364
u32 addr2;
6465
bool reset_pmc;
6566
int (*reset_eng)(struct nvkm_falcon *);

‎drivers/gpu/drm/nouveau/include/nvkm/engine/sec2.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,4 +23,5 @@ struct nvkm_sec2 {
2323
int gp102_sec2_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_sec2 **);
2424
int gp108_sec2_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_sec2 **);
2525
int tu102_sec2_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_sec2 **);
26+
int ga102_sec2_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_sec2 **);
2627
#endif

‎drivers/gpu/drm/nouveau/include/nvkm/subdev/acr.h

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -67,6 +67,7 @@ int gp108_acr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct
6767
int gp10b_acr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_acr **);
6868
int gv100_acr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_acr **);
6969
int tu102_acr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_acr **);
70+
int ga102_acr_new(struct nvkm_device *, enum nvkm_subdev_type, int inst, struct nvkm_acr **);
7071

7172
struct nvkm_acr_lsfw {
7273
const struct nvkm_acr_lsf_func *func;
@@ -79,6 +80,7 @@ struct nvkm_acr_lsfw {
7980

8081
const struct firmware *sig;
8182

83+
bool secure_bootloader;
8284
u32 bootloader_size;
8385
u32 bootloader_imem_offset;
8486

@@ -89,10 +91,19 @@ struct nvkm_acr_lsfw {
8991
u32 app_resident_code_size;
9092
u32 app_resident_data_offset;
9193
u32 app_resident_data_size;
94+
u32 app_imem_offset;
95+
u32 app_dmem_offset;
9296

9397
u32 ucode_size;
9498
u32 data_size;
9599

100+
u32 fuse_ver;
101+
u32 engine_id;
102+
u32 ucode_id;
103+
u32 sig_size;
104+
u32 sig_nr;
105+
u8 *sigs;
106+
96107
struct {
97108
u32 lsb;
98109
u32 img;
@@ -123,6 +134,12 @@ int
123134
nvkm_acr_lsfw_load_sig_image_desc_v1(struct nvkm_subdev *, struct nvkm_falcon *,
124135
enum nvkm_acr_lsf_id, const char *path,
125136
int ver, const struct nvkm_acr_lsf_func *);
137+
138+
int
139+
nvkm_acr_lsfw_load_sig_image_desc_v2(struct nvkm_subdev *, struct nvkm_falcon *,
140+
enum nvkm_acr_lsf_id, const char *path,
141+
int ver, const struct nvkm_acr_lsf_func *);
142+
126143
int
127144
nvkm_acr_lsfw_load_bl_inst_data_sig(struct nvkm_subdev *, struct nvkm_falcon *,
128145
enum nvkm_acr_lsf_id, const char *path,

‎drivers/gpu/drm/nouveau/include/nvkm/subdev/gsp.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -12,4 +12,5 @@ struct nvkm_gsp {
1212
};
1313

1414
int gv100_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **);
15+
int ga102_gsp_new(struct nvkm_device *, enum nvkm_subdev_type, int, struct nvkm_gsp **);
1516
#endif

‎drivers/gpu/drm/nouveau/nvkm/engine/device/base.c

Lines changed: 15 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2596,12 +2596,14 @@ nv170_chipset = {
25962596
static const struct nvkm_device_chip
25972597
nv172_chipset = {
25982598
.name = "GA102",
2599+
.acr = { 0x00000001, ga102_acr_new },
25992600
.bar = { 0x00000001, tu102_bar_new },
26002601
.bios = { 0x00000001, nvkm_bios_new },
26012602
.devinit = { 0x00000001, ga100_devinit_new },
26022603
.fault = { 0x00000001, tu102_fault_new },
26032604
.fb = { 0x00000001, ga102_fb_new },
26042605
.gpio = { 0x00000001, ga102_gpio_new },
2606+
.gsp = { 0x00000001, ga102_gsp_new },
26052607
.i2c = { 0x00000001, gm200_i2c_new },
26062608
.imem = { 0x00000001, nv50_instmem_new },
26072609
.mc = { 0x00000001, ga100_mc_new },
@@ -2616,17 +2618,20 @@ nv172_chipset = {
26162618
.dma = { 0x00000001, gv100_dma_new },
26172619
.fifo = { 0x00000001, ga102_fifo_new },
26182620
.nvdec = { 0x00000001, ga102_nvdec_new },
2621+
.sec2 = { 0x00000001, ga102_sec2_new },
26192622
};
26202623

26212624
static const struct nvkm_device_chip
26222625
nv173_chipset = {
26232626
.name = "GA103",
2627+
.acr = { 0x00000001, ga102_acr_new },
26242628
.bar = { 0x00000001, tu102_bar_new },
26252629
.bios = { 0x00000001, nvkm_bios_new },
26262630
.devinit = { 0x00000001, ga100_devinit_new },
26272631
.fault = { 0x00000001, tu102_fault_new },
26282632
.fb = { 0x00000001, ga102_fb_new },
26292633
.gpio = { 0x00000001, ga102_gpio_new },
2634+
.gsp = { 0x00000001, ga102_gsp_new },
26302635
.i2c = { 0x00000001, gm200_i2c_new },
26312636
.imem = { 0x00000001, nv50_instmem_new },
26322637
.mc = { 0x00000001, ga100_mc_new },
@@ -2641,17 +2646,20 @@ nv173_chipset = {
26412646
.dma = { 0x00000001, gv100_dma_new },
26422647
.fifo = { 0x00000001, ga102_fifo_new },
26432648
.nvdec = { 0x00000001, ga102_nvdec_new },
2649+
.sec2 = { 0x00000001, ga102_sec2_new },
26442650
};
26452651

26462652
static const struct nvkm_device_chip
26472653
nv174_chipset = {
26482654
.name = "GA104",
2655+
.acr = { 0x00000001, ga102_acr_new },
26492656
.bar = { 0x00000001, tu102_bar_new },
26502657
.bios = { 0x00000001, nvkm_bios_new },
26512658
.devinit = { 0x00000001, ga100_devinit_new },
26522659
.fault = { 0x00000001, tu102_fault_new },
26532660
.fb = { 0x00000001, ga102_fb_new },
26542661
.gpio = { 0x00000001, ga102_gpio_new },
2662+
.gsp = { 0x00000001, ga102_gsp_new },
26552663
.i2c = { 0x00000001, gm200_i2c_new },
26562664
.imem = { 0x00000001, nv50_instmem_new },
26572665
.mc = { 0x00000001, ga100_mc_new },
@@ -2666,17 +2674,20 @@ nv174_chipset = {
26662674
.dma = { 0x00000001, gv100_dma_new },
26672675
.fifo = { 0x00000001, ga102_fifo_new },
26682676
.nvdec = { 0x00000001, ga102_nvdec_new },
2677+
.sec2 = { 0x00000001, ga102_sec2_new },
26692678
};
26702679

26712680
static const struct nvkm_device_chip
26722681
nv176_chipset = {
26732682
.name = "GA106",
2683+
.acr = { 0x00000001, ga102_acr_new },
26742684
.bar = { 0x00000001, tu102_bar_new },
26752685
.bios = { 0x00000001, nvkm_bios_new },
26762686
.devinit = { 0x00000001, ga100_devinit_new },
26772687
.fault = { 0x00000001, tu102_fault_new },
26782688
.fb = { 0x00000001, ga102_fb_new },
26792689
.gpio = { 0x00000001, ga102_gpio_new },
2690+
.gsp = { 0x00000001, ga102_gsp_new },
26802691
.i2c = { 0x00000001, gm200_i2c_new },
26812692
.imem = { 0x00000001, nv50_instmem_new },
26822693
.mc = { 0x00000001, ga100_mc_new },
@@ -2691,17 +2702,20 @@ nv176_chipset = {
26912702
.dma = { 0x00000001, gv100_dma_new },
26922703
.fifo = { 0x00000001, ga102_fifo_new },
26932704
.nvdec = { 0x00000001, ga102_nvdec_new },
2705+
.sec2 = { 0x00000001, ga102_sec2_new },
26942706
};
26952707

26962708
static const struct nvkm_device_chip
26972709
nv177_chipset = {
26982710
.name = "GA107",
2711+
.acr = { 0x00000001, ga102_acr_new },
26992712
.bar = { 0x00000001, tu102_bar_new },
27002713
.bios = { 0x00000001, nvkm_bios_new },
27012714
.devinit = { 0x00000001, ga100_devinit_new },
27022715
.fault = { 0x00000001, tu102_fault_new },
27032716
.fb = { 0x00000001, ga102_fb_new },
27042717
.gpio = { 0x00000001, ga102_gpio_new },
2718+
.gsp = { 0x00000001, ga102_gsp_new },
27052719
.i2c = { 0x00000001, gm200_i2c_new },
27062720
.imem = { 0x00000001, nv50_instmem_new },
27072721
.mc = { 0x00000001, ga100_mc_new },
@@ -2716,6 +2730,7 @@ nv177_chipset = {
27162730
.dma = { 0x00000001, gv100_dma_new },
27172731
.fifo = { 0x00000001, ga102_fifo_new },
27182732
.nvdec = { 0x00000001, ga102_nvdec_new },
2733+
.sec2 = { 0x00000001, ga102_sec2_new },
27192734
};
27202735

27212736
struct nvkm_subdev *

‎drivers/gpu/drm/nouveau/nvkm/engine/sec2/Kbuild

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3,3 +3,4 @@ nvkm-y += nvkm/engine/sec2/base.o
33
nvkm-y += nvkm/engine/sec2/gp102.o
44
nvkm-y += nvkm/engine/sec2/gp108.o
55
nvkm-y += nvkm/engine/sec2/tu102.o
6+
nvkm-y += nvkm/engine/sec2/ga102.o

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