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airliedairlied
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Merge tag 'drm-intel-fixes-2024-04-04' of https://anongit.freedesktop.org/git/drm/drm-intel into drm-fixes
Display fixes: - A few DisplayPort related fixes (Imre, Arun, Ankit, Ville) - eDP PSR fixes (Jouni) Core/GT fixes: - Remove some VM space restrictions on older platforms (Andi) - Disable automatic load CCS load balancing (Andi) Signed-off-by: Dave Airlie <[email protected]> From: Rodrigo Vivi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents a5b5ab3 + 99f8550 commit 4c85957

15 files changed

+185
-42
lines changed

‎drivers/gpu/drm/i915/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -118,6 +118,7 @@ gt-y += \
118118
gt/intel_ggtt_fencing.o \
119119
gt/intel_gt.o \
120120
gt/intel_gt_buffer_pool.o \
121+
gt/intel_gt_ccs_mode.o \
121122
gt/intel_gt_clock_utils.o \
122123
gt/intel_gt_debugfs.o \
123124
gt/intel_gt_engines_debugfs.o \

‎drivers/gpu/drm/i915/display/intel_display.c

Lines changed: 0 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2709,15 +2709,6 @@ static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
27092709
*/
27102710
intel_de_write(dev_priv, PIPESRC(pipe),
27112711
PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
2712-
2713-
if (!crtc_state->enable_psr2_su_region_et)
2714-
return;
2715-
2716-
width = drm_rect_width(&crtc_state->psr2_su_area);
2717-
height = drm_rect_height(&crtc_state->psr2_su_area);
2718-
2719-
intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(pipe),
2720-
PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
27212712
}
27222713

27232714
static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)

‎drivers/gpu/drm/i915/display/intel_display_device.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -47,6 +47,7 @@ struct drm_printer;
4747
#define HAS_DPT(i915) (DISPLAY_VER(i915) >= 13)
4848
#define HAS_DSB(i915) (DISPLAY_INFO(i915)->has_dsb)
4949
#define HAS_DSC(__i915) (DISPLAY_RUNTIME_INFO(__i915)->has_dsc)
50+
#define HAS_DSC_MST(__i915) (DISPLAY_VER(__i915) >= 12 && HAS_DSC(__i915))
5051
#define HAS_FBC(i915) (DISPLAY_RUNTIME_INFO(i915)->fbc_mask != 0)
5152
#define HAS_FPGA_DBG_UNCLAIMED(i915) (DISPLAY_INFO(i915)->has_fpga_dbg)
5253
#define HAS_FW_BLC(i915) (DISPLAY_VER(i915) >= 3)

‎drivers/gpu/drm/i915/display/intel_display_types.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1423,6 +1423,8 @@ struct intel_crtc_state {
14231423

14241424
u32 psr2_man_track_ctl;
14251425

1426+
u32 pipe_srcsz_early_tpt;
1427+
14261428
struct drm_rect psr2_su_area;
14271429

14281430
/* Variable Refresh Rate state */

‎drivers/gpu/drm/i915/display/intel_dp.c

Lines changed: 7 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -499,7 +499,7 @@ intel_dp_set_source_rates(struct intel_dp *intel_dp)
499499
/* The values must be in increasing order */
500500
static const int mtl_rates[] = {
501501
162000, 216000, 243000, 270000, 324000, 432000, 540000, 675000,
502-
810000, 1000000, 1350000, 2000000,
502+
810000, 1000000, 2000000,
503503
};
504504
static const int icl_rates[] = {
505505
162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000,
@@ -1422,7 +1422,8 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
14221422
if (DISPLAY_VER(dev_priv) >= 12)
14231423
return true;
14241424

1425-
if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A)
1425+
if (DISPLAY_VER(dev_priv) == 11 && encoder->port != PORT_A &&
1426+
!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DP_MST))
14261427
return true;
14271428

14281429
return false;
@@ -1917,8 +1918,9 @@ icl_dsc_compute_link_config(struct intel_dp *intel_dp,
19171918
dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
19181919

19191920
for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp); i++) {
1920-
if (valid_dsc_bpp[i] < dsc_min_bpp ||
1921-
valid_dsc_bpp[i] > dsc_max_bpp)
1921+
if (valid_dsc_bpp[i] < dsc_min_bpp)
1922+
continue;
1923+
if (valid_dsc_bpp[i] > dsc_max_bpp)
19221924
break;
19231925

19241926
ret = dsc_compute_link_config(intel_dp,
@@ -6557,6 +6559,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
65576559
intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
65586560
else
65596561
intel_connector->get_hw_state = intel_connector_get_hw_state;
6562+
intel_connector->sync_state = intel_dp_connector_sync_state;
65606563

65616564
if (!intel_edp_init_connector(intel_dp, intel_connector)) {
65626565
intel_dp_aux_fini(intel_dp);

‎drivers/gpu/drm/i915/display/intel_dp_mst.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1355,7 +1355,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
13551355
return 0;
13561356
}
13571357

1358-
if (DISPLAY_VER(dev_priv) >= 10 &&
1358+
if (HAS_DSC_MST(dev_priv) &&
13591359
drm_dp_sink_supports_dsc(intel_connector->dp.dsc_dpcd)) {
13601360
/*
13611361
* TBD pass the connector BPC,

‎drivers/gpu/drm/i915/display/intel_psr.c

Lines changed: 56 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -1994,6 +1994,7 @@ static void psr_force_hw_tracking_exit(struct intel_dp *intel_dp)
19941994

19951995
void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_state)
19961996
{
1997+
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
19971998
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
19981999
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
19992000
struct intel_encoder *encoder;
@@ -2013,6 +2014,12 @@ void intel_psr2_program_trans_man_trk_ctl(const struct intel_crtc_state *crtc_st
20132014

20142015
intel_de_write(dev_priv, PSR2_MAN_TRK_CTL(cpu_transcoder),
20152016
crtc_state->psr2_man_track_ctl);
2017+
2018+
if (!crtc_state->enable_psr2_su_region_et)
2019+
return;
2020+
2021+
intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(crtc->pipe),
2022+
crtc_state->pipe_srcsz_early_tpt);
20162023
}
20172024

20182025
static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
@@ -2051,6 +2058,20 @@ static void psr2_man_trk_ctl_calc(struct intel_crtc_state *crtc_state,
20512058
crtc_state->psr2_man_track_ctl = val;
20522059
}
20532060

2061+
static u32 psr2_pipe_srcsz_early_tpt_calc(struct intel_crtc_state *crtc_state,
2062+
bool full_update)
2063+
{
2064+
int width, height;
2065+
2066+
if (!crtc_state->enable_psr2_su_region_et || full_update)
2067+
return 0;
2068+
2069+
width = drm_rect_width(&crtc_state->psr2_su_area);
2070+
height = drm_rect_height(&crtc_state->psr2_su_area);
2071+
2072+
return PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1);
2073+
}
2074+
20542075
static void clip_area_update(struct drm_rect *overlap_damage_area,
20552076
struct drm_rect *damage_area,
20562077
struct drm_rect *pipe_src)
@@ -2095,21 +2116,36 @@ static void intel_psr2_sel_fetch_pipe_alignment(struct intel_crtc_state *crtc_st
20952116
* cursor fully when cursor is in SU area.
20962117
*/
20972118
static void
2098-
intel_psr2_sel_fetch_et_alignment(struct intel_crtc_state *crtc_state,
2099-
struct intel_plane_state *cursor_state)
2119+
intel_psr2_sel_fetch_et_alignment(struct intel_atomic_state *state,
2120+
struct intel_crtc *crtc)
21002121
{
2101-
struct drm_rect inter;
2122+
struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
2123+
struct intel_plane_state *new_plane_state;
2124+
struct intel_plane *plane;
2125+
int i;
21022126

2103-
if (!crtc_state->enable_psr2_su_region_et ||
2104-
!cursor_state->uapi.visible)
2127+
if (!crtc_state->enable_psr2_su_region_et)
21052128
return;
21062129

2107-
inter = crtc_state->psr2_su_area;
2108-
if (!drm_rect_intersect(&inter, &cursor_state->uapi.dst))
2109-
return;
2130+
for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
2131+
struct drm_rect inter;
21102132

2111-
clip_area_update(&crtc_state->psr2_su_area, &cursor_state->uapi.dst,
2112-
&crtc_state->pipe_src);
2133+
if (new_plane_state->uapi.crtc != crtc_state->uapi.crtc)
2134+
continue;
2135+
2136+
if (plane->id != PLANE_CURSOR)
2137+
continue;
2138+
2139+
if (!new_plane_state->uapi.visible)
2140+
continue;
2141+
2142+
inter = crtc_state->psr2_su_area;
2143+
if (!drm_rect_intersect(&inter, &new_plane_state->uapi.dst))
2144+
continue;
2145+
2146+
clip_area_update(&crtc_state->psr2_su_area, &new_plane_state->uapi.dst,
2147+
&crtc_state->pipe_src);
2148+
}
21132149
}
21142150

21152151
/*
@@ -2152,8 +2188,7 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
21522188
{
21532189
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
21542190
struct intel_crtc_state *crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
2155-
struct intel_plane_state *new_plane_state, *old_plane_state,
2156-
*cursor_plane_state = NULL;
2191+
struct intel_plane_state *new_plane_state, *old_plane_state;
21572192
struct intel_plane *plane;
21582193
bool full_update = false;
21592194
int i, ret;
@@ -2238,13 +2273,6 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
22382273
damaged_area.x2 += new_plane_state->uapi.dst.x1 - src.x1;
22392274

22402275
clip_area_update(&crtc_state->psr2_su_area, &damaged_area, &crtc_state->pipe_src);
2241-
2242-
/*
2243-
* Cursor plane new state is stored to adjust su area to cover
2244-
* cursor are fully.
2245-
*/
2246-
if (plane->id == PLANE_CURSOR)
2247-
cursor_plane_state = new_plane_state;
22482276
}
22492277

22502278
/*
@@ -2273,9 +2301,13 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
22732301
if (ret)
22742302
return ret;
22752303

2276-
/* Adjust su area to cover cursor fully as necessary */
2277-
if (cursor_plane_state)
2278-
intel_psr2_sel_fetch_et_alignment(crtc_state, cursor_plane_state);
2304+
/*
2305+
* Adjust su area to cover cursor fully as necessary (early
2306+
* transport). This needs to be done after
2307+
* drm_atomic_add_affected_planes to ensure visible cursor is added into
2308+
* affected planes even when cursor is not updated by itself.
2309+
*/
2310+
intel_psr2_sel_fetch_et_alignment(state, crtc);
22792311

22802312
intel_psr2_sel_fetch_pipe_alignment(crtc_state);
22812313

@@ -2338,6 +2370,8 @@ int intel_psr2_sel_fetch_update(struct intel_atomic_state *state,
23382370

23392371
skip_sel_fetch_set_loop:
23402372
psr2_man_trk_ctl_calc(crtc_state, full_update);
2373+
crtc_state->pipe_srcsz_early_tpt =
2374+
psr2_pipe_srcsz_early_tpt_calc(crtc_state, full_update);
23412375
return 0;
23422376
}
23432377

‎drivers/gpu/drm/i915/gt/gen8_ppgtt.c

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -961,6 +961,9 @@ static int gen8_init_rsvd(struct i915_address_space *vm)
961961
struct i915_vma *vma;
962962
int ret;
963963

964+
if (!intel_gt_needs_wa_16018031267(vm->gt))
965+
return 0;
966+
964967
/* The memory will be used only by GPU. */
965968
obj = i915_gem_object_create_lmem(i915, PAGE_SIZE,
966969
I915_BO_ALLOC_VOLATILE |

‎drivers/gpu/drm/i915/gt/intel_engine_cs.c

Lines changed: 17 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -908,6 +908,23 @@ static intel_engine_mask_t init_engine_mask(struct intel_gt *gt)
908908
info->engine_mask &= ~BIT(GSC0);
909909
}
910910

911+
/*
912+
* Do not create the command streamer for CCS slices beyond the first.
913+
* All the workload submitted to the first engine will be shared among
914+
* all the slices.
915+
*
916+
* Once the user will be allowed to customize the CCS mode, then this
917+
* check needs to be removed.
918+
*/
919+
if (IS_DG2(gt->i915)) {
920+
u8 first_ccs = __ffs(CCS_MASK(gt));
921+
922+
/* Mask off all the CCS engine */
923+
info->engine_mask &= ~GENMASK(CCS3, CCS0);
924+
/* Put back in the first CCS engine */
925+
info->engine_mask |= BIT(_CCS(first_ccs));
926+
}
927+
911928
return info->engine_mask;
912929
}
913930

‎drivers/gpu/drm/i915/gt/intel_gt.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1024,6 +1024,12 @@ enum i915_map_type intel_gt_coherent_map_type(struct intel_gt *gt,
10241024
return I915_MAP_WC;
10251025
}
10261026

1027+
bool intel_gt_needs_wa_16018031267(struct intel_gt *gt)
1028+
{
1029+
/* Wa_16018031267, Wa_16018063123 */
1030+
return IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 55), IP_VER(12, 71));
1031+
}
1032+
10271033
bool intel_gt_needs_wa_22016122933(struct intel_gt *gt)
10281034
{
10291035
return MEDIA_VER_FULL(gt->i915) == IP_VER(13, 0) && gt->type == GT_MEDIA;

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