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Merge tag 'pci-v6.2-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
Pull PCI fixes from Bjorn Helgaas: - Move to a shared PCI git tree (Bjorn Helgaas) - Add Krzysztof Wilczyński as another PCI maintainer (Lorenzo Pieralisi) - Revert a couple ASPM patches to fix suspend/resume regressions (Bjorn Helgaas) * tag 'pci-v6.2-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci: Revert "PCI/ASPM: Refactor L1 PM Substates Control Register programming" Revert "PCI/ASPM: Save L1 PM Substates Capability for suspend/resume" MAINTAINERS: Promote Krzysztof to PCI controller maintainer MAINTAINERS: Move to shared PCI tree
2 parents 4f72a26 + ff209ec commit 4cfd5af

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‎MAINTAINERS

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -16120,15 +16120,15 @@ F: drivers/pci/controller/pci-v3-semi.c
1612016120

1612116121
PCI ENDPOINT SUBSYSTEM
1612216122
M: Lorenzo Pieralisi <[email protected]>
16123-
R: Krzysztof Wilczyński <[email protected]>
16123+
M: Krzysztof Wilczyński <[email protected]>
1612416124
R: Manivannan Sadhasivam <[email protected]>
1612516125
R: Kishon Vijay Abraham I <[email protected]>
1612616126
L: [email protected]
1612716127
S: Supported
1612816128
Q: https://patchwork.kernel.org/project/linux-pci/list/
1612916129
B: https://bugzilla.kernel.org
1613016130
C: irc://irc.oftc.net/linux-pci
16131-
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git
16131+
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git
1613216132
F: Documentation/PCI/endpoint/*
1613316133
F: Documentation/misc-devices/pci-endpoint-test.rst
1613416134
F: drivers/misc/pci_endpoint_test.c
@@ -16163,7 +16163,7 @@ S: Supported
1616316163
Q: https://patchwork.kernel.org/project/linux-pci/list/
1616416164
B: https://bugzilla.kernel.org
1616516165
C: irc://irc.oftc.net/linux-pci
16166-
T: git git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git
16166+
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git
1616716167
F: Documentation/driver-api/pci/p2pdma.rst
1616816168
F: drivers/pci/p2pdma.c
1616916169
F: include/linux/pci-p2pdma.h
@@ -16185,14 +16185,14 @@ F: drivers/pci/controller/pci-xgene-msi.c
1618516185

1618616186
PCI NATIVE HOST BRIDGE AND ENDPOINT DRIVERS
1618716187
M: Lorenzo Pieralisi <[email protected]>
16188+
M: Krzysztof Wilczyński <[email protected]>
1618816189
R: Rob Herring <[email protected]>
16189-
R: Krzysztof Wilczyński <[email protected]>
1619016190
L: [email protected]
1619116191
S: Supported
1619216192
Q: https://patchwork.kernel.org/project/linux-pci/list/
1619316193
B: https://bugzilla.kernel.org
1619416194
C: irc://irc.oftc.net/linux-pci
16195-
T: git git://git.kernel.org/pub/scm/linux/kernel/git/lpieralisi/pci.git
16195+
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git
1619616196
F: Documentation/devicetree/bindings/pci/
1619716197
F: drivers/pci/controller/
1619816198
F: drivers/pci/pci-bridge-emul.c
@@ -16205,7 +16205,7 @@ S: Supported
1620516205
Q: https://patchwork.kernel.org/project/linux-pci/list/
1620616206
B: https://bugzilla.kernel.org
1620716207
C: irc://irc.oftc.net/linux-pci
16208-
T: git git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git
16208+
T: git git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git
1620916209
F: Documentation/PCI/
1621016210
F: Documentation/devicetree/bindings/pci/
1621116211
F: arch/x86/kernel/early-quirks.c

‎drivers/pci/pci.c

Lines changed: 0 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1665,7 +1665,6 @@ int pci_save_state(struct pci_dev *dev)
16651665
return i;
16661666

16671667
pci_save_ltr_state(dev);
1668-
pci_save_aspm_l1ss_state(dev);
16691668
pci_save_dpc_state(dev);
16701669
pci_save_aer_state(dev);
16711670
pci_save_ptm_state(dev);
@@ -1772,7 +1771,6 @@ void pci_restore_state(struct pci_dev *dev)
17721771
* LTR itself (in the PCIe capability).
17731772
*/
17741773
pci_restore_ltr_state(dev);
1775-
pci_restore_aspm_l1ss_state(dev);
17761774

17771775
pci_restore_pcie_state(dev);
17781776
pci_restore_pasid_state(dev);
@@ -3465,11 +3463,6 @@ void pci_allocate_cap_save_buffers(struct pci_dev *dev)
34653463
if (error)
34663464
pci_err(dev, "unable to allocate suspend buffer for LTR\n");
34673465

3468-
error = pci_add_ext_cap_save_buffer(dev, PCI_EXT_CAP_ID_L1SS,
3469-
2 * sizeof(u32));
3470-
if (error)
3471-
pci_err(dev, "unable to allocate suspend buffer for ASPM-L1SS\n");
3472-
34733466
pci_allocate_vc_save_buffers(dev);
34743467
}
34753468

‎drivers/pci/pci.h

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -566,14 +566,10 @@ bool pcie_wait_for_link(struct pci_dev *pdev, bool active);
566566
void pcie_aspm_init_link_state(struct pci_dev *pdev);
567567
void pcie_aspm_exit_link_state(struct pci_dev *pdev);
568568
void pcie_aspm_powersave_config_link(struct pci_dev *pdev);
569-
void pci_save_aspm_l1ss_state(struct pci_dev *dev);
570-
void pci_restore_aspm_l1ss_state(struct pci_dev *dev);
571569
#else
572570
static inline void pcie_aspm_init_link_state(struct pci_dev *pdev) { }
573571
static inline void pcie_aspm_exit_link_state(struct pci_dev *pdev) { }
574572
static inline void pcie_aspm_powersave_config_link(struct pci_dev *pdev) { }
575-
static inline void pci_save_aspm_l1ss_state(struct pci_dev *dev) { }
576-
static inline void pci_restore_aspm_l1ss_state(struct pci_dev *dev) { }
577573
#endif
578574

579575
#ifdef CONFIG_PCIE_ECRC

‎drivers/pci/pcie/aspm.c

Lines changed: 34 additions & 77 deletions
Original file line numberDiff line numberDiff line change
@@ -470,31 +470,6 @@ static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
470470
pci_write_config_dword(pdev, pos, val);
471471
}
472472

473-
static void aspm_program_l1ss(struct pci_dev *dev, u32 ctl1, u32 ctl2)
474-
{
475-
u16 l1ss = dev->l1ss;
476-
u32 l1_2_enable;
477-
478-
/*
479-
* Per PCIe r6.0, sec 5.5.4, T_POWER_ON in PCI_L1SS_CTL2 must be
480-
* programmed prior to setting the L1.2 enable bits in PCI_L1SS_CTL1.
481-
*/
482-
pci_write_config_dword(dev, l1ss + PCI_L1SS_CTL2, ctl2);
483-
484-
/*
485-
* In addition, Common_Mode_Restore_Time and LTR_L1.2_THRESHOLD in
486-
* PCI_L1SS_CTL1 must be programmed *before* setting the L1.2
487-
* enable bits, even though they're all in PCI_L1SS_CTL1.
488-
*/
489-
l1_2_enable = ctl1 & PCI_L1SS_CTL1_L1_2_MASK;
490-
ctl1 &= ~PCI_L1SS_CTL1_L1_2_MASK;
491-
492-
pci_write_config_dword(dev, l1ss + PCI_L1SS_CTL1, ctl1);
493-
if (l1_2_enable)
494-
pci_write_config_dword(dev, l1ss + PCI_L1SS_CTL1,
495-
ctl1 | l1_2_enable);
496-
}
497-
498473
/* Calculate L1.2 PM substate timing parameters */
499474
static void aspm_calc_l1ss_info(struct pcie_link_state *link,
500475
u32 parent_l1ss_cap, u32 child_l1ss_cap)
@@ -504,6 +479,7 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
504479
u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
505480
u32 ctl1 = 0, ctl2 = 0;
506481
u32 pctl1, pctl2, cctl1, cctl2;
482+
u32 pl1_2_enables, cl1_2_enables;
507483

508484
if (!(link->aspm_support & ASPM_STATE_L1_2_MASK))
509485
return;
@@ -552,21 +528,39 @@ static void aspm_calc_l1ss_info(struct pcie_link_state *link,
552528
ctl2 == pctl2 && ctl2 == cctl2)
553529
return;
554530

555-
pctl1 &= ~(PCI_L1SS_CTL1_CM_RESTORE_TIME |
556-
PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
557-
PCI_L1SS_CTL1_LTR_L12_TH_SCALE);
558-
pctl1 |= (ctl1 & (PCI_L1SS_CTL1_CM_RESTORE_TIME |
559-
PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
560-
PCI_L1SS_CTL1_LTR_L12_TH_SCALE));
561-
aspm_program_l1ss(parent, pctl1, ctl2);
562-
563-
cctl1 &= ~(PCI_L1SS_CTL1_CM_RESTORE_TIME |
564-
PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
565-
PCI_L1SS_CTL1_LTR_L12_TH_SCALE);
566-
cctl1 |= (ctl1 & (PCI_L1SS_CTL1_CM_RESTORE_TIME |
567-
PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
568-
PCI_L1SS_CTL1_LTR_L12_TH_SCALE));
569-
aspm_program_l1ss(child, cctl1, ctl2);
531+
/* Disable L1.2 while updating. See PCIe r5.0, sec 5.5.4, 7.8.3.3 */
532+
pl1_2_enables = pctl1 & PCI_L1SS_CTL1_L1_2_MASK;
533+
cl1_2_enables = cctl1 & PCI_L1SS_CTL1_L1_2_MASK;
534+
535+
if (pl1_2_enables || cl1_2_enables) {
536+
pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
537+
PCI_L1SS_CTL1_L1_2_MASK, 0);
538+
pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
539+
PCI_L1SS_CTL1_L1_2_MASK, 0);
540+
}
541+
542+
/* Program T_POWER_ON times in both ports */
543+
pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2);
544+
pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2);
545+
546+
/* Program Common_Mode_Restore_Time in upstream device */
547+
pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
548+
PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1);
549+
550+
/* Program LTR_L1.2_THRESHOLD time in both ports */
551+
pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
552+
PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
553+
PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
554+
pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
555+
PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
556+
PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
557+
558+
if (pl1_2_enables || cl1_2_enables) {
559+
pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, 0,
560+
pl1_2_enables);
561+
pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, 0,
562+
cl1_2_enables);
563+
}
570564
}
571565

572566
static void aspm_l1ss_init(struct pcie_link_state *link)
@@ -757,43 +751,6 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
757751
PCI_L1SS_CTL1_L1SS_MASK, val);
758752
}
759753

760-
void pci_save_aspm_l1ss_state(struct pci_dev *dev)
761-
{
762-
struct pci_cap_saved_state *save_state;
763-
u16 l1ss = dev->l1ss;
764-
u32 *cap;
765-
766-
if (!l1ss)
767-
return;
768-
769-
save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_L1SS);
770-
if (!save_state)
771-
return;
772-
773-
cap = (u32 *)&save_state->cap.data[0];
774-
pci_read_config_dword(dev, l1ss + PCI_L1SS_CTL2, cap++);
775-
pci_read_config_dword(dev, l1ss + PCI_L1SS_CTL1, cap++);
776-
}
777-
778-
void pci_restore_aspm_l1ss_state(struct pci_dev *dev)
779-
{
780-
struct pci_cap_saved_state *save_state;
781-
u32 *cap, ctl1, ctl2;
782-
u16 l1ss = dev->l1ss;
783-
784-
if (!l1ss)
785-
return;
786-
787-
save_state = pci_find_saved_ext_cap(dev, PCI_EXT_CAP_ID_L1SS);
788-
if (!save_state)
789-
return;
790-
791-
cap = (u32 *)&save_state->cap.data[0];
792-
ctl2 = *cap++;
793-
ctl1 = *cap;
794-
aspm_program_l1ss(dev, ctl1, ctl2);
795-
}
796-
797754
static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
798755
{
799756
pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,

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