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Itamar-Gozlankuba-moo
Itamar-Gozlan
authored and
kuba-moo
committed
net/mlx5: DR, add support for ConnectX-8 steering
Add support for a new steering format version that is implemented by ConnectX-8. Except for several differences, the STEv3 is identical to STEv2, so for most callbacks STEv3 context struct will call STEv2 functions. Signed-off-by: Itamar Gozlan <[email protected]> Signed-off-by: Yevgeny Kliteynik <[email protected]> Signed-off-by: Tariq Toukan <[email protected]> Link: https://patch.msgid.link/[email protected] Signed-off-by: Jakub Kicinski <[email protected]>
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‎drivers/net/ethernet/mellanox/mlx5/core/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -123,6 +123,7 @@ mlx5_core-$(CONFIG_MLX5_SW_STEERING) += steering/sws/dr_domain.o \
123123
steering/sws/dr_ste_v0.o \
124124
steering/sws/dr_ste_v1.o \
125125
steering/sws/dr_ste_v2.o \
126+
steering/sws/dr_ste_v3.o \
126127
steering/sws/dr_cmd.o \
127128
steering/sws/dr_fw.o \
128129
steering/sws/dr_action.o \

‎drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_domain.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
#define DR_DOMAIN_SW_STEERING_SUPPORTED(dmn, dmn_type) \
99
((dmn)->info.caps.dmn_type##_sw_owner || \
1010
((dmn)->info.caps.dmn_type##_sw_owner_v2 && \
11-
(dmn)->info.caps.sw_format_ver <= MLX5_STEERING_FORMAT_CONNECTX_7))
11+
(dmn)->info.caps.sw_format_ver <= MLX5_STEERING_FORMAT_CONNECTX_8))
1212

1313
bool mlx5dr_domain_is_support_ptrn_arg(struct mlx5dr_domain *dmn)
1414
{

‎drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ste.c

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1458,6 +1458,8 @@ struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx(u8 version)
14581458
return mlx5dr_ste_get_ctx_v1();
14591459
else if (version == MLX5_STEERING_FORMAT_CONNECTX_7)
14601460
return mlx5dr_ste_get_ctx_v2();
1461+
else if (version == MLX5_STEERING_FORMAT_CONNECTX_8)
1462+
return mlx5dr_ste_get_ctx_v3();
14611463

14621464
return NULL;
14631465
}

‎drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ste.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -217,5 +217,6 @@ struct mlx5dr_ste_ctx {
217217
struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx_v0(void);
218218
struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx_v1(void);
219219
struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx_v2(void);
220+
struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx_v3(void);
220221

221222
#endif /* _DR_STE_ */

‎drivers/net/ethernet/mellanox/mlx5/core/steering/sws/dr_ste_v3.c

Lines changed: 221 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,221 @@
1+
// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
2+
/* Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved. */
3+
4+
#include "dr_ste_v1.h"
5+
#include "dr_ste_v2.h"
6+
7+
static void dr_ste_v3_set_encap(u8 *hw_ste_p, u8 *d_action,
8+
u32 reformat_id, int size)
9+
{
10+
MLX5_SET(ste_double_action_insert_with_ptr_v3, d_action, action_id,
11+
DR_STE_V1_ACTION_ID_INSERT_POINTER);
12+
/* The hardware expects here size in words (2 byte) */
13+
MLX5_SET(ste_double_action_insert_with_ptr_v3, d_action, size, size / 2);
14+
MLX5_SET(ste_double_action_insert_with_ptr_v3, d_action, pointer, reformat_id);
15+
MLX5_SET(ste_double_action_insert_with_ptr_v3, d_action, attributes,
16+
DR_STE_V1_ACTION_INSERT_PTR_ATTR_ENCAP);
17+
dr_ste_v1_set_reparse(hw_ste_p);
18+
}
19+
20+
static void dr_ste_v3_set_push_vlan(u8 *ste, u8 *d_action,
21+
u32 vlan_hdr)
22+
{
23+
MLX5_SET(ste_double_action_insert_with_inline_v3, d_action, action_id,
24+
DR_STE_V1_ACTION_ID_INSERT_INLINE);
25+
/* The hardware expects here offset to vlan header in words (2 byte) */
26+
MLX5_SET(ste_double_action_insert_with_inline_v3, d_action, start_offset,
27+
HDR_LEN_L2_MACS >> 1);
28+
MLX5_SET(ste_double_action_insert_with_inline_v3, d_action, inline_data, vlan_hdr);
29+
dr_ste_v1_set_reparse(ste);
30+
}
31+
32+
static void dr_ste_v3_set_pop_vlan(u8 *hw_ste_p, u8 *s_action,
33+
u8 vlans_num)
34+
{
35+
MLX5_SET(ste_single_action_remove_header_size_v3, s_action,
36+
action_id, DR_STE_V1_ACTION_ID_REMOVE_BY_SIZE);
37+
MLX5_SET(ste_single_action_remove_header_size_v3, s_action,
38+
start_anchor, DR_STE_HEADER_ANCHOR_1ST_VLAN);
39+
/* The hardware expects here size in words (2 byte) */
40+
MLX5_SET(ste_single_action_remove_header_size_v3, s_action,
41+
remove_size, (HDR_LEN_L2_VLAN >> 1) * vlans_num);
42+
43+
dr_ste_v1_set_reparse(hw_ste_p);
44+
}
45+
46+
static void dr_ste_v3_set_encap_l3(u8 *hw_ste_p,
47+
u8 *frst_s_action,
48+
u8 *scnd_d_action,
49+
u32 reformat_id,
50+
int size)
51+
{
52+
/* Remove L2 headers */
53+
MLX5_SET(ste_single_action_remove_header_v3, frst_s_action, action_id,
54+
DR_STE_V1_ACTION_ID_REMOVE_HEADER_TO_HEADER);
55+
MLX5_SET(ste_single_action_remove_header_v3, frst_s_action, end_anchor,
56+
DR_STE_HEADER_ANCHOR_IPV6_IPV4);
57+
58+
/* Encapsulate with given reformat ID */
59+
MLX5_SET(ste_double_action_insert_with_ptr_v3, scnd_d_action, action_id,
60+
DR_STE_V1_ACTION_ID_INSERT_POINTER);
61+
/* The hardware expects here size in words (2 byte) */
62+
MLX5_SET(ste_double_action_insert_with_ptr_v3, scnd_d_action, size, size / 2);
63+
MLX5_SET(ste_double_action_insert_with_ptr_v3, scnd_d_action, pointer, reformat_id);
64+
MLX5_SET(ste_double_action_insert_with_ptr_v3, scnd_d_action, attributes,
65+
DR_STE_V1_ACTION_INSERT_PTR_ATTR_ENCAP);
66+
67+
dr_ste_v1_set_reparse(hw_ste_p);
68+
}
69+
70+
static void dr_ste_v3_set_rx_decap(u8 *hw_ste_p, u8 *s_action)
71+
{
72+
MLX5_SET(ste_single_action_remove_header_v3, s_action, action_id,
73+
DR_STE_V1_ACTION_ID_REMOVE_HEADER_TO_HEADER);
74+
MLX5_SET(ste_single_action_remove_header_v3, s_action, decap, 1);
75+
MLX5_SET(ste_single_action_remove_header_v3, s_action, vni_to_cqe, 1);
76+
MLX5_SET(ste_single_action_remove_header_v3, s_action, end_anchor,
77+
DR_STE_HEADER_ANCHOR_INNER_MAC);
78+
79+
dr_ste_v1_set_reparse(hw_ste_p);
80+
}
81+
82+
static int
83+
dr_ste_v3_set_action_decap_l3_list(void *data, u32 data_sz,
84+
u8 *hw_action, u32 hw_action_sz,
85+
uint16_t *used_hw_action_num)
86+
{
87+
u8 padded_data[DR_STE_L2_HDR_MAX_SZ] = {};
88+
void *data_ptr = padded_data;
89+
u16 used_actions = 0;
90+
u32 inline_data_sz;
91+
u32 i;
92+
93+
if (hw_action_sz / DR_STE_ACTION_DOUBLE_SZ < DR_STE_DECAP_L3_ACTION_NUM)
94+
return -EINVAL;
95+
96+
inline_data_sz =
97+
MLX5_FLD_SZ_BYTES(ste_double_action_insert_with_inline_v3, inline_data);
98+
99+
/* Add an alignment padding */
100+
memcpy(padded_data + data_sz % inline_data_sz, data, data_sz);
101+
102+
/* Remove L2L3 outer headers */
103+
MLX5_SET(ste_single_action_remove_header_v3, hw_action, action_id,
104+
DR_STE_V1_ACTION_ID_REMOVE_HEADER_TO_HEADER);
105+
MLX5_SET(ste_single_action_remove_header_v3, hw_action, decap, 1);
106+
MLX5_SET(ste_single_action_remove_header_v3, hw_action, vni_to_cqe, 1);
107+
MLX5_SET(ste_single_action_remove_header_v3, hw_action, end_anchor,
108+
DR_STE_HEADER_ANCHOR_INNER_IPV6_IPV4);
109+
hw_action += DR_STE_ACTION_DOUBLE_SZ;
110+
used_actions++; /* Remove and NOP are a single double action */
111+
112+
/* Point to the last dword of the header */
113+
data_ptr += (data_sz / inline_data_sz) * inline_data_sz;
114+
115+
/* Add the new header using inline action 4Byte at a time, the header
116+
* is added in reversed order to the beginning of the packet to avoid
117+
* incorrect parsing by the HW. Since header is 14B or 18B an extra
118+
* two bytes are padded and later removed.
119+
*/
120+
for (i = 0; i < data_sz / inline_data_sz + 1; i++) {
121+
void *addr_inline;
122+
123+
MLX5_SET(ste_double_action_insert_with_inline_v3, hw_action, action_id,
124+
DR_STE_V1_ACTION_ID_INSERT_INLINE);
125+
/* The hardware expects here offset to words (2 bytes) */
126+
MLX5_SET(ste_double_action_insert_with_inline_v3, hw_action, start_offset, 0);
127+
128+
/* Copy bytes one by one to avoid endianness problem */
129+
addr_inline = MLX5_ADDR_OF(ste_double_action_insert_with_inline_v3,
130+
hw_action, inline_data);
131+
memcpy(addr_inline, data_ptr - i * inline_data_sz, inline_data_sz);
132+
hw_action += DR_STE_ACTION_DOUBLE_SZ;
133+
used_actions++;
134+
}
135+
136+
/* Remove first 2 extra bytes */
137+
MLX5_SET(ste_single_action_remove_header_size_v3, hw_action, action_id,
138+
DR_STE_V1_ACTION_ID_REMOVE_BY_SIZE);
139+
MLX5_SET(ste_single_action_remove_header_size_v3, hw_action, start_offset, 0);
140+
/* The hardware expects here size in words (2 bytes) */
141+
MLX5_SET(ste_single_action_remove_header_size_v3, hw_action, remove_size, 1);
142+
used_actions++;
143+
144+
*used_hw_action_num = used_actions;
145+
146+
return 0;
147+
}
148+
149+
static struct mlx5dr_ste_ctx ste_ctx_v3 = {
150+
/* Builders */
151+
.build_eth_l2_src_dst_init = &dr_ste_v1_build_eth_l2_src_dst_init,
152+
.build_eth_l3_ipv6_src_init = &dr_ste_v1_build_eth_l3_ipv6_src_init,
153+
.build_eth_l3_ipv6_dst_init = &dr_ste_v1_build_eth_l3_ipv6_dst_init,
154+
.build_eth_l3_ipv4_5_tuple_init = &dr_ste_v1_build_eth_l3_ipv4_5_tuple_init,
155+
.build_eth_l2_src_init = &dr_ste_v1_build_eth_l2_src_init,
156+
.build_eth_l2_dst_init = &dr_ste_v1_build_eth_l2_dst_init,
157+
.build_eth_l2_tnl_init = &dr_ste_v1_build_eth_l2_tnl_init,
158+
.build_eth_l3_ipv4_misc_init = &dr_ste_v1_build_eth_l3_ipv4_misc_init,
159+
.build_eth_ipv6_l3_l4_init = &dr_ste_v1_build_eth_ipv6_l3_l4_init,
160+
.build_mpls_init = &dr_ste_v1_build_mpls_init,
161+
.build_tnl_gre_init = &dr_ste_v1_build_tnl_gre_init,
162+
.build_tnl_mpls_init = &dr_ste_v1_build_tnl_mpls_init,
163+
.build_tnl_mpls_over_udp_init = &dr_ste_v1_build_tnl_mpls_over_udp_init,
164+
.build_tnl_mpls_over_gre_init = &dr_ste_v1_build_tnl_mpls_over_gre_init,
165+
.build_icmp_init = &dr_ste_v1_build_icmp_init,
166+
.build_general_purpose_init = &dr_ste_v1_build_general_purpose_init,
167+
.build_eth_l4_misc_init = &dr_ste_v1_build_eth_l4_misc_init,
168+
.build_tnl_vxlan_gpe_init = &dr_ste_v1_build_flex_parser_tnl_vxlan_gpe_init,
169+
.build_tnl_geneve_init = &dr_ste_v1_build_flex_parser_tnl_geneve_init,
170+
.build_tnl_geneve_tlv_opt_init = &dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_init,
171+
.build_tnl_geneve_tlv_opt_exist_init =
172+
&dr_ste_v1_build_flex_parser_tnl_geneve_tlv_opt_exist_init,
173+
.build_register_0_init = &dr_ste_v1_build_register_0_init,
174+
.build_register_1_init = &dr_ste_v1_build_register_1_init,
175+
.build_src_gvmi_qpn_init = &dr_ste_v1_build_src_gvmi_qpn_init,
176+
.build_flex_parser_0_init = &dr_ste_v1_build_flex_parser_0_init,
177+
.build_flex_parser_1_init = &dr_ste_v1_build_flex_parser_1_init,
178+
.build_tnl_gtpu_init = &dr_ste_v1_build_flex_parser_tnl_gtpu_init,
179+
.build_tnl_header_0_1_init = &dr_ste_v1_build_tnl_header_0_1_init,
180+
.build_tnl_gtpu_flex_parser_0_init = &dr_ste_v1_build_tnl_gtpu_flex_parser_0_init,
181+
.build_tnl_gtpu_flex_parser_1_init = &dr_ste_v1_build_tnl_gtpu_flex_parser_1_init,
182+
183+
/* Getters and Setters */
184+
.ste_init = &dr_ste_v1_init,
185+
.set_next_lu_type = &dr_ste_v1_set_next_lu_type,
186+
.get_next_lu_type = &dr_ste_v1_get_next_lu_type,
187+
.is_miss_addr_set = &dr_ste_v1_is_miss_addr_set,
188+
.set_miss_addr = &dr_ste_v1_set_miss_addr,
189+
.get_miss_addr = &dr_ste_v1_get_miss_addr,
190+
.set_hit_addr = &dr_ste_v1_set_hit_addr,
191+
.set_byte_mask = &dr_ste_v1_set_byte_mask,
192+
.get_byte_mask = &dr_ste_v1_get_byte_mask,
193+
194+
/* Actions */
195+
.actions_caps = DR_STE_CTX_ACTION_CAP_TX_POP |
196+
DR_STE_CTX_ACTION_CAP_RX_PUSH |
197+
DR_STE_CTX_ACTION_CAP_RX_ENCAP,
198+
.set_actions_rx = &dr_ste_v1_set_actions_rx,
199+
.set_actions_tx = &dr_ste_v1_set_actions_tx,
200+
.modify_field_arr_sz = ARRAY_SIZE(dr_ste_v2_action_modify_field_arr),
201+
.modify_field_arr = dr_ste_v2_action_modify_field_arr,
202+
.set_action_set = &dr_ste_v1_set_action_set,
203+
.set_action_add = &dr_ste_v1_set_action_add,
204+
.set_action_copy = &dr_ste_v1_set_action_copy,
205+
.set_action_decap_l3_list = &dr_ste_v3_set_action_decap_l3_list,
206+
.alloc_modify_hdr_chunk = &dr_ste_v1_alloc_modify_hdr_ptrn_arg,
207+
.dealloc_modify_hdr_chunk = &dr_ste_v1_free_modify_hdr_ptrn_arg,
208+
/* Actions bit set */
209+
.set_encap = &dr_ste_v3_set_encap,
210+
.set_push_vlan = &dr_ste_v3_set_push_vlan,
211+
.set_pop_vlan = &dr_ste_v3_set_pop_vlan,
212+
.set_rx_decap = &dr_ste_v3_set_rx_decap,
213+
.set_encap_l3 = &dr_ste_v3_set_encap_l3,
214+
/* Send */
215+
.prepare_for_postsend = &dr_ste_v1_prepare_for_postsend,
216+
};
217+
218+
struct mlx5dr_ste_ctx *mlx5dr_ste_get_ctx_v3(void)
219+
{
220+
return &ste_ctx_v3;
221+
}

‎drivers/net/ethernet/mellanox/mlx5/core/steering/sws/mlx5_ifc_dr.h

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -600,4 +600,44 @@ struct mlx5_ifc_ste_double_action_aso_v1_bits {
600600
};
601601
};
602602

603+
struct mlx5_ifc_ste_single_action_remove_header_v3_bits {
604+
u8 action_id[0x8];
605+
u8 start_anchor[0x7];
606+
u8 end_anchor[0x7];
607+
u8 reserved_at_16[0x1];
608+
u8 outer_l4_remove[0x1];
609+
u8 reserved_at_18[0x4];
610+
u8 decap[0x1];
611+
u8 vni_to_cqe[0x1];
612+
u8 qos_profile[0x2];
613+
};
614+
615+
struct mlx5_ifc_ste_single_action_remove_header_size_v3_bits {
616+
u8 action_id[0x8];
617+
u8 start_anchor[0x7];
618+
u8 start_offset[0x8];
619+
u8 outer_l4_remove[0x1];
620+
u8 reserved_at_18[0x2];
621+
u8 remove_size[0x6];
622+
};
623+
624+
struct mlx5_ifc_ste_double_action_insert_with_inline_v3_bits {
625+
u8 action_id[0x8];
626+
u8 start_anchor[0x7];
627+
u8 start_offset[0x8];
628+
u8 reserved_at_17[0x9];
629+
630+
u8 inline_data[0x20];
631+
};
632+
633+
struct mlx5_ifc_ste_double_action_insert_with_ptr_v3_bits {
634+
u8 action_id[0x8];
635+
u8 start_anchor[0x7];
636+
u8 start_offset[0x8];
637+
u8 size[0x6];
638+
u8 attributes[0x3];
639+
640+
u8 pointer[0x20];
641+
};
642+
603643
#endif /* MLX5_IFC_DR_H */

‎drivers/net/ethernet/mellanox/mlx5/core/steering/sws/mlx5dr.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -160,7 +160,7 @@ mlx5dr_is_supported(struct mlx5_core_dev *dev)
160160
(MLX5_CAP_ESW_FLOWTABLE_FDB(dev, sw_owner) ||
161161
(MLX5_CAP_ESW_FLOWTABLE_FDB(dev, sw_owner_v2) &&
162162
(MLX5_CAP_GEN(dev, steering_format_version) <=
163-
MLX5_STEERING_FORMAT_CONNECTX_7)));
163+
MLX5_STEERING_FORMAT_CONNECTX_8)));
164164
}
165165

166166
/* buddy functions & structure */

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