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Merge tag 'samsung-clk-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung clk driver updates from Krzysztof Kozlowski: - Exynos850: Add clock for Thermal Management Unit - Exynos7885: Fix duplicated ID in the header, add missing TOP PLLs and add clocks for USB block in the FSYS clock controller - ExynosAutov9: Add DPUM clock controller - ExynosAutov920: Add new (first) clock controllers: TOP and PERIC0 (and a bit more complete bindings) * tag 'samsung-clk-6.12' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: clk: samsung: add top clock support for ExynosAuto v920 SoC clk: samsung: clk-pll: Add support for pll_531x dt-bindings: clock: add ExynosAuto v920 SoC CMU bindings clk: samsung: exynos7885: Add USB related clocks to CMU_FSYS clk: samsung: clk-pll: Add support for pll_1418x clk: samsung: exynosautov9: add dpum clock support dt-bindings: clock: exynosautov9: add dpum clock clk: samsung: exynos7885: Add missing MUX clocks from PLLs in CMU_TOP clk: samsung: exynos7885: Update CLKS_NR_FSYS after bindings fix dt-bindings: clock: exynos7885: Add indices for USB clocks dt-bindings: clock: exynos7885: Add CMU_TOP PLL MUX indices dt-bindings: clock: exynos7885: Fix duplicated binding clk: samsung: exynos850: Add TMU clock dt-bindings: clock: exynos850: Add TMU clock
2 parents 8400291 + 485e13f commit 4e52054

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‎Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml

Lines changed: 19 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,7 @@ properties:
3535
- samsung,exynosautov9-cmu-top
3636
- samsung,exynosautov9-cmu-busmc
3737
- samsung,exynosautov9-cmu-core
38+
- samsung,exynosautov9-cmu-dpum
3839
- samsung,exynosautov9-cmu-fsys0
3940
- samsung,exynosautov9-cmu-fsys1
4041
- samsung,exynosautov9-cmu-fsys2
@@ -109,6 +110,24 @@ allOf:
109110
- const: oscclk
110111
- const: dout_clkcmu_core_bus
111112

113+
- if:
114+
properties:
115+
compatible:
116+
contains:
117+
const: samsung,exynosautov9-cmu-dpum
118+
119+
then:
120+
properties:
121+
clocks:
122+
items:
123+
- description: External reference clock (26 MHz)
124+
- description: DPU Main bus clock (from CMU_TOP)
125+
126+
clock-names:
127+
items:
128+
- const: oscclk
129+
- const: bus
130+
112131
- if:
113132
properties:
114133
compatible:

‎Documentation/devicetree/bindings/clock/samsung,exynosautov920-clock.yaml

Lines changed: 162 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,162 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/clock/samsung,exynosautov920-clock.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: Samsung ExynosAuto v920 SoC clock controller
8+
9+
maintainers:
10+
- Sunyeal Hong <[email protected]>
11+
- Chanwoo Choi <[email protected]>
12+
- Krzysztof Kozlowski <[email protected]>
13+
- Sylwester Nawrocki <[email protected]>
14+
15+
description: |
16+
ExynosAuto v920 clock controller is comprised of several CMU units, generating
17+
clocks for different domains. Those CMU units are modeled as separate device
18+
tree nodes, and might depend on each other. Root clocks in that clock tree are
19+
two external clocks:: OSCCLK/XTCXO (38.4 MHz) and RTCCLK/XrtcXTI (32768 Hz).
20+
The external OSCCLK must be defined as fixed-rate clock in dts.
21+
22+
CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
23+
dividers; all other clocks of function blocks (other CMUs) are usually
24+
derived from CMU_TOP.
25+
26+
Each clock is assigned an identifier and client nodes can use this identifier
27+
to specify the clock which they consume. All clocks available for usage
28+
in clock consumer nodes are defined as preprocessor macros in
29+
'include/dt-bindings/clock/samsung,exynosautov920.h' header.
30+
31+
properties:
32+
compatible:
33+
enum:
34+
- samsung,exynosautov920-cmu-top
35+
- samsung,exynosautov920-cmu-peric0
36+
- samsung,exynosautov920-cmu-peric1
37+
- samsung,exynosautov920-cmu-misc
38+
- samsung,exynosautov920-cmu-hsi0
39+
- samsung,exynosautov920-cmu-hsi1
40+
41+
clocks:
42+
minItems: 1
43+
maxItems: 4
44+
45+
clock-names:
46+
minItems: 1
47+
maxItems: 4
48+
49+
"#clock-cells":
50+
const: 1
51+
52+
reg:
53+
maxItems: 1
54+
55+
allOf:
56+
- if:
57+
properties:
58+
compatible:
59+
contains:
60+
const: samsung,exynosautov920-cmu-top
61+
62+
then:
63+
properties:
64+
clocks:
65+
items:
66+
- description: External reference clock (38.4 MHz)
67+
68+
clock-names:
69+
items:
70+
- const: oscclk
71+
72+
- if:
73+
properties:
74+
compatible:
75+
contains:
76+
enum:
77+
- samsung,exynosautov920-cmu-peric0
78+
- samsung,exynosautov920-cmu-peric1
79+
80+
then:
81+
properties:
82+
clocks:
83+
items:
84+
- description: External reference clock (38.4 MHz)
85+
- description: CMU_PERICn NOC clock (from CMU_TOP)
86+
- description: CMU_PERICn IP clock (from CMU_TOP)
87+
88+
clock-names:
89+
items:
90+
- const: oscclk
91+
- const: noc
92+
- const: ip
93+
94+
- if:
95+
properties:
96+
compatible:
97+
enum:
98+
- samsung,exynosautov920-cmu-misc
99+
- samsung,exynosautov920-cmu-hsi0
100+
101+
then:
102+
properties:
103+
clocks:
104+
items:
105+
- description: External reference clock (38.4 MHz)
106+
- description: CMU_MISC/CMU_HSI0 NOC clock (from CMU_TOP)
107+
108+
clock-names:
109+
items:
110+
- const: oscclk
111+
- const: noc
112+
113+
- if:
114+
properties:
115+
compatible:
116+
contains:
117+
const: samsung,exynosautov920-cmu-hsi1
118+
119+
then:
120+
properties:
121+
clocks:
122+
items:
123+
- description: External reference clock (38.4 MHz)
124+
- description: CMU_HSI1 NOC clock (from CMU_TOP)
125+
- description: CMU_HSI1 USBDRD clock (from CMU_TOP)
126+
- description: CMU_HSI1 MMC_CARD clock (from CMU_TOP)
127+
128+
clock-names:
129+
items:
130+
- const: oscclk
131+
- const: noc
132+
- const: usbdrd
133+
- const: mmc_card
134+
135+
required:
136+
- compatible
137+
- "#clock-cells"
138+
- clocks
139+
- clock-names
140+
- reg
141+
142+
additionalProperties: false
143+
144+
examples:
145+
# Clock controller node for CMU_PERIC0
146+
- |
147+
#include <dt-bindings/clock/samsung,exynosautov920.h>
148+
149+
cmu_peric0: clock-controller@10800000 {
150+
compatible = "samsung,exynosautov920-cmu-peric0";
151+
reg = <0x10800000 0x8000>;
152+
#clock-cells = <1>;
153+
154+
clocks = <&xtcxo>,
155+
<&cmu_top DOUT_CLKCMU_PERIC0_NOC>,
156+
<&cmu_top DOUT_CLKCMU_PERIC0_IP>;
157+
clock-names = "oscclk",
158+
"noc",
159+
"ip";
160+
};
161+
162+
...

‎drivers/clk/samsung/Makefile

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -21,6 +21,7 @@ obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7.o
2121
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos7885.o
2222
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynos850.o
2323
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov9.o
24+
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-exynosautov920.o
2425
obj-$(CONFIG_EXYNOS_ARM64_COMMON_CLK) += clk-gs101.o
2526
obj-$(CONFIG_S3C64XX_COMMON_CLK) += clk-s3c64xx.o
2627
obj-$(CONFIG_S5PV210_COMMON_CLK) += clk-s5pv210.o clk-s5pv210-audss.o

‎drivers/clk/samsung/clk-exynos7885.c

Lines changed: 73 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -17,10 +17,10 @@
1717
#include "clk-exynos-arm64.h"
1818

1919
/* NOTE: Must be equal to the last clock ID increased by one */
20-
#define CLKS_NR_TOP (CLK_GOUT_FSYS_USB30DRD + 1)
20+
#define CLKS_NR_TOP (CLK_MOUT_SHARED1_PLL + 1)
2121
#define CLKS_NR_CORE (CLK_GOUT_TREX_P_CORE_PCLK_P_CORE + 1)
2222
#define CLKS_NR_PERI (CLK_GOUT_WDT1_PCLK + 1)
23-
#define CLKS_NR_FSYS (CLK_GOUT_MMC_SDIO_SDCLKIN + 1)
23+
#define CLKS_NR_FSYS (CLK_FSYS_USB30DRD_REF_CLK + 1)
2424

2525
/* ---- CMU_TOP ------------------------------------------------------------- */
2626

@@ -162,6 +162,10 @@ static const struct samsung_pll_clock top_pll_clks[] __initconst = {
162162
NULL),
163163
};
164164

165+
/* List of parent clocks for Muxes in CMU_TOP */
166+
PNAME(mout_shared0_pll_p) = { "oscclk", "fout_shared0_pll" };
167+
PNAME(mout_shared1_pll_p) = { "oscclk", "fout_shared1_pll" };
168+
165169
/* List of parent clocks for Muxes in CMU_TOP: for CMU_CORE */
166170
PNAME(mout_core_bus_p) = { "dout_shared0_div2", "dout_shared1_div2",
167171
"dout_shared0_div3", "dout_shared0_div3" };
@@ -189,6 +193,12 @@ PNAME(mout_fsys_mmc_sdio_p) = { "dout_shared0_div2", "dout_shared1_div2" };
189193
PNAME(mout_fsys_usb30drd_p) = { "dout_shared0_div4", "dout_shared1_div4" };
190194

191195
static const struct samsung_mux_clock top_mux_clks[] __initconst = {
196+
/* TOP */
197+
MUX(CLK_MOUT_SHARED0_PLL, "mout_shared0_pll", mout_shared0_pll_p,
198+
PLL_CON0_PLL_SHARED0, 4, 1),
199+
MUX(CLK_MOUT_SHARED1_PLL, "mout_shared1_pll", mout_shared1_pll_p,
200+
PLL_CON0_PLL_SHARED1, 4, 1),
201+
192202
/* CORE */
193203
MUX(CLK_MOUT_CORE_BUS, "mout_core_bus", mout_core_bus_p,
194204
CLK_CON_MUX_MUX_CLKCMU_CORE_BUS, 0, 2),
@@ -232,17 +242,17 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = {
232242

233243
static const struct samsung_div_clock top_div_clks[] __initconst = {
234244
/* TOP */
235-
DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "fout_shared0_pll",
245+
DIV(CLK_DOUT_SHARED0_DIV2, "dout_shared0_div2", "mout_shared0_pll",
236246
CLK_CON_DIV_PLL_SHARED0_DIV2, 0, 1),
237-
DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "fout_shared0_pll",
247+
DIV(CLK_DOUT_SHARED0_DIV3, "dout_shared0_div3", "mout_shared0_pll",
238248
CLK_CON_DIV_PLL_SHARED0_DIV3, 0, 2),
239249
DIV(CLK_DOUT_SHARED0_DIV4, "dout_shared0_div4", "dout_shared0_div2",
240250
CLK_CON_DIV_PLL_SHARED0_DIV4, 0, 1),
241-
DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "fout_shared0_pll",
251+
DIV(CLK_DOUT_SHARED0_DIV5, "dout_shared0_div5", "mout_shared0_pll",
242252
CLK_CON_DIV_PLL_SHARED0_DIV5, 0, 3),
243-
DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "fout_shared1_pll",
253+
DIV(CLK_DOUT_SHARED1_DIV2, "dout_shared1_div2", "mout_shared1_pll",
244254
CLK_CON_DIV_PLL_SHARED1_DIV2, 0, 1),
245-
DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "fout_shared1_pll",
255+
DIV(CLK_DOUT_SHARED1_DIV3, "dout_shared1_div3", "mout_shared1_pll",
246256
CLK_CON_DIV_PLL_SHARED1_DIV3, 0, 2),
247257
DIV(CLK_DOUT_SHARED1_DIV4, "dout_shared1_div4", "dout_shared1_div2",
248258
CLK_CON_DIV_PLL_SHARED1_DIV4, 0, 1),
@@ -676,30 +686,56 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
676686
/* ---- CMU_FSYS ------------------------------------------------------------ */
677687

678688
/* Register Offset definitions for CMU_FSYS (0x13400000) */
679-
#define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER 0x0100
680-
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER 0x0120
681-
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER 0x0140
682-
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER 0x0160
683-
#define PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER 0x0180
684-
#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK 0x2030
685-
#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN 0x2034
686-
#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK 0x2038
687-
#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN 0x203c
688-
#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK 0x2040
689-
#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN 0x2044
689+
#define PLL_LOCKTIME_PLL_USB 0x0000
690+
#define PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER 0x0100
691+
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER 0x0120
692+
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER 0x0140
693+
#define PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER 0x0160
694+
#define PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER 0x0180
695+
#define PLL_CON0_PLL_USB 0x01a0
696+
#define CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE 0x200c
697+
#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK 0x2030
698+
#define CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN 0x2034
699+
#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK 0x2038
700+
#define CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN 0x203c
701+
#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK 0x2040
702+
#define CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN 0x2044
703+
#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL 0x2068
704+
#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0 0x206c
705+
#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1 0x2070
706+
#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY 0x2074
707+
#define CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK 0x2078
690708

691709
static const unsigned long fsys_clk_regs[] __initconst = {
710+
PLL_LOCKTIME_PLL_USB,
692711
PLL_CON0_MUX_CLKCMU_FSYS_BUS_USER,
693712
PLL_CON0_MUX_CLKCMU_FSYS_MMC_CARD_USER,
694713
PLL_CON0_MUX_CLKCMU_FSYS_MMC_EMBD_USER,
695714
PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,
696715
PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,
716+
PLL_CON0_PLL_USB,
717+
CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE,
697718
CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK,
698719
CLK_CON_GAT_GOUT_FSYS_MMC_CARD_SDCLKIN,
699720
CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_I_ACLK,
700721
CLK_CON_GAT_GOUT_FSYS_MMC_EMBD_SDCLKIN,
701722
CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_I_ACLK,
702723
CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,
724+
CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL,
725+
CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0,
726+
CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1,
727+
CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY,
728+
CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK,
729+
};
730+
731+
static const struct samsung_pll_rate_table pll_usb_rate_table[] __initconst = {
732+
PLL_35XX_RATE(26 * MHZ, 50000000U, 400, 13, 4),
733+
};
734+
735+
static const struct samsung_pll_clock fsys_pll_clks[] __initconst = {
736+
PLL(pll_1418x, CLK_FOUT_USB_PLL, "fout_usb_pll", "oscclk",
737+
PLL_LOCKTIME_PLL_USB, PLL_CON0_PLL_USB,
738+
pll_usb_rate_table),
703739
};
704740

705741
/* List of parent clocks for Muxes in CMU_FSYS */
@@ -708,6 +744,7 @@ PNAME(mout_fsys_mmc_card_user_p) = { "oscclk", "dout_fsys_mmc_card" };
708744
PNAME(mout_fsys_mmc_embd_user_p) = { "oscclk", "dout_fsys_mmc_embd" };
709745
PNAME(mout_fsys_mmc_sdio_user_p) = { "oscclk", "dout_fsys_mmc_sdio" };
710746
PNAME(mout_fsys_usb30drd_user_p) = { "oscclk", "dout_fsys_usb30drd" };
747+
PNAME(mout_usb_pll_p) = { "oscclk", "fout_usb_pll" };
711748

712749
static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
713750
MUX(CLK_MOUT_FSYS_BUS_USER, "mout_fsys_bus_user", mout_fsys_bus_user_p,
@@ -721,12 +758,16 @@ static const struct samsung_mux_clock fsys_mux_clks[] __initconst = {
721758
MUX_F(CLK_MOUT_FSYS_MMC_SDIO_USER, "mout_fsys_mmc_sdio_user",
722759
mout_fsys_mmc_sdio_user_p, PLL_CON0_MUX_CLKCMU_FSYS_MMC_SDIO_USER,
723760
4, 1, CLK_SET_RATE_PARENT, 0),
724-
MUX_F(CLK_MOUT_FSYS_USB30DRD_USER, "mout_fsys_usb30drd_user",
761+
MUX(CLK_MOUT_FSYS_USB30DRD_USER, "mout_fsys_usb30drd_user",
725762
mout_fsys_usb30drd_user_p, PLL_CON0_MUX_CLKCMU_FSYS_USB30DRD_USER,
726-
4, 1, CLK_SET_RATE_PARENT, 0),
763+
4, 1),
764+
nMUX_F(CLK_MOUT_USB_PLL, "mout_usb_pll", mout_usb_pll_p,
765+
PLL_CON0_PLL_USB, 4, 1, CLK_SET_RATE_PARENT, 0),
727766
};
728767

729768
static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
769+
GATE(CLK_FSYS_USB20PHY_CLKCORE, "clk_fsys_usb20phy_clkcore", "mout_usb_pll",
770+
CLK_CON_GAT_CLK_FSYS_USB20PHY_CLKCORE, 21, CLK_SET_RATE_PARENT, 0),
730771
GATE(CLK_GOUT_MMC_CARD_ACLK, "gout_mmc_card_aclk", "mout_fsys_bus_user",
731772
CLK_CON_GAT_GOUT_FSYS_MMC_CARD_I_ACLK, 21, 0, 0),
732773
GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin",
@@ -742,9 +783,21 @@ static const struct samsung_gate_clock fsys_gate_clks[] __initconst = {
742783
GATE(CLK_GOUT_MMC_SDIO_SDCLKIN, "gout_mmc_sdio_sdclkin",
743784
"mout_fsys_mmc_sdio_user", CLK_CON_GAT_GOUT_FSYS_MMC_SDIO_SDCLKIN,
744785
21, CLK_SET_RATE_PARENT, 0),
786+
GATE(CLK_FSYS_USB30DRD_ACLK_20PHYCTRL, "clk_fsys_usb30drd_aclk_20phyctrl",
787+
"mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_20PHYCTRL, 21, 0, 0),
788+
GATE(CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_0, "clk_fsys_usb30drd_aclk_30phyctrl_0",
789+
"mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_0, 21, 0, 0),
790+
GATE(CLK_FSYS_USB30DRD_ACLK_30PHYCTRL_1, "clk_fsys_usb30drd_aclk_30phyctrl_1",
791+
"mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_ACLK_30PHYCTRL_1, 21, 0, 0),
792+
GATE(CLK_FSYS_USB30DRD_BUS_CLK_EARLY, "clk_fsys_usb30drd_bus_clk_early",
793+
"mout_fsys_bus_user", CLK_CON_GAT_GOUT_FSYS_USB30DRD_BUS_CLK_EARLY, 21, 0, 0),
794+
GATE(CLK_FSYS_USB30DRD_REF_CLK, "clk_fsys_usb30drd_ref_clk", "mout_fsys_usb30drd_user",
795+
CLK_CON_GAT_GOUT_FSYS_USB30DRD_REF_CLK, 21, 0, 0),
745796
};
746797

747798
static const struct samsung_cmu_info fsys_cmu_info __initconst = {
799+
.pll_clks = fsys_pll_clks,
800+
.nr_pll_clks = ARRAY_SIZE(fsys_pll_clks),
748801
.mux_clks = fsys_mux_clks,
749802
.nr_mux_clks = ARRAY_SIZE(fsys_mux_clks),
750803
.gate_clks = fsys_gate_clks,

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