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Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM SoC late updates from Olof Johansson: "This is some material that we picked up into our tree late, or that had more complex dependencies on more than one topic branch that makes sense to keep separately. - TI support for secure accelerators and hwrng on OMAP4/5 - TI camera changes for dra7 and am437x and SGX improvement due to better reset control support on am335x, am437x and dra7 - Davinci moves to proper clocksource on DM365, and regulator/audio improvements for DM365 and DM644x eval boards" * tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (32 commits) ARM: dts: omap4-droid4: Enable hdq for droid4 ds250x 1-wire battery nvmem ARM: dts: motorola-cpcap-mapphone: Configure calibration interrupt ARM: dts: Configure interconnect target module for am437x sgx ARM: dts: Configure sgx for dra7 ARM: dts: Configure rstctrl reset for am335x SGX ARM: dts: dra7: Add ti-sysc node for VPE ARM: dts: dra7: add vpe clkctrl node ARM: dts: am43x-epos-evm: Add VPFE and OV2659 entries ARM: dts: am437x-sk-evm: Add VPFE and OV2659 entries ARM: dts: am43xx: add support for clkout1 clock arm: dts: dra76-evm: Add CAL and OV5640 nodes arm: dtsi: dra76x: Add CAL dtsi node arm: dts: dra72-evm-common: Add entries for the CSI2 cameras ARM: dts: DRA72: Add CAL dtsi node ARM: dts: dra7-l4: Add ti-sysc node for CAM ARM: OMAP: DRA7xx: Make CAM clock domain SWSUP only ARM: dts: dra7: add cam clkctrl node ARM: OMAP2+: Drop legacy platform data for omap4 des ARM: OMAP2+: Drop legacy platform data for omap4 sham ARM: OMAP2+: Drop legacy platform data for omap4 aes ...
2 parents 5939224 + a832eb2 commit 4ef1a30

35 files changed

+697
-675
lines changed

‎arch/arm/boot/dts/am33xx.dtsi

Lines changed: 25 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -496,6 +496,31 @@
496496
dma-names = "tx", "rx";
497497
};
498498
};
499+
500+
target-module@56000000 {
501+
compatible = "ti,sysc-omap4", "ti,sysc";
502+
reg = <0x5600fe00 0x4>,
503+
<0x5600fe10 0x4>;
504+
reg-names = "rev", "sysc";
505+
ti,sysc-midle = <SYSC_IDLE_FORCE>,
506+
<SYSC_IDLE_NO>,
507+
<SYSC_IDLE_SMART>;
508+
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
509+
<SYSC_IDLE_NO>,
510+
<SYSC_IDLE_SMART>;
511+
clocks = <&gfx_l3_clkctrl AM3_GFX_L3_GFX_CLKCTRL 0>;
512+
clock-names = "fck";
513+
resets = <&prm_gfx 0>;
514+
reset-names = "rstctrl";
515+
#address-cells = <1>;
516+
#size-cells = <1>;
517+
ranges = <0 0x56000000 0x1000000>;
518+
519+
/*
520+
* Closed source PowerVR driver, no child device
521+
* binding or driver in mainline
522+
*/
523+
};
499524
};
500525
};
501526

‎arch/arm/boot/dts/am4372.dtsi

Lines changed: 20 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -445,6 +445,26 @@
445445
pool;
446446
};
447447
};
448+
449+
target-module@56000000 {
450+
compatible = "ti,sysc-omap4", "ti,sysc";
451+
reg = <0x5600fe00 0x4>,
452+
<0x5600fe10 0x4>;
453+
reg-names = "rev", "sysc";
454+
ti,sysc-midle = <SYSC_IDLE_FORCE>,
455+
<SYSC_IDLE_NO>,
456+
<SYSC_IDLE_SMART>;
457+
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
458+
<SYSC_IDLE_NO>,
459+
<SYSC_IDLE_SMART>;
460+
clocks = <&gfx_l3_clkctrl AM4_GFX_L3_GFX_CLKCTRL 0>;
461+
clock-names = "fck";
462+
resets = <&prm_gfx 0>;
463+
reset-names = "rstctrl";
464+
#address-cells = <1>;
465+
#size-cells = <1>;
466+
ranges = <0 0x56000000 0x1000000>;
467+
};
448468
};
449469
};
450470

‎arch/arm/boot/dts/am437x-sk-evm.dts

Lines changed: 26 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -272,6 +272,12 @@
272272
>;
273273
};
274274

275+
clkout1_pin: pinmux_clkout1_pin {
276+
pinctrl-single,pins = <
277+
0x270 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* XDMA_EVENT_INTR0/CLKOUT1 */
278+
>;
279+
};
280+
275281
cpsw_default: cpsw_default {
276282
pinctrl-single,pins = <
277283
/* Slave 1 */
@@ -593,6 +599,25 @@
593599
pinctrl-0 = <&i2c1_pins>;
594600
clock-frequency = <400000>;
595601

602+
ov2659@30 {
603+
compatible = "ovti,ov2659";
604+
reg = <0x30>;
605+
pinctrl-names = "default";
606+
pinctrl-0 = <&clkout1_pin>;
607+
608+
clocks = <&clkout1_mux_ck>;
609+
clock-names = "xvclk";
610+
assigned-clocks = <&clkout1_mux_ck>;
611+
assigned-clock-parents = <&clkout1_osc_div_ck>;
612+
613+
port {
614+
ov2659_1: endpoint {
615+
remote-endpoint = <&vpfe0_ep>;
616+
link-frequencies = /bits/ 64 <70000000>;
617+
};
618+
};
619+
};
620+
596621
edt-ft5306@38 {
597622
status = "okay";
598623
compatible = "edt,edt-ft5306", "edt,edt-ft5x06";
@@ -877,7 +902,7 @@
877902
/* Camera port */
878903
port {
879904
vpfe0_ep: endpoint {
880-
/* remote-endpoint = <&sensor>; add once we have it */
905+
remote-endpoint = <&ov2659_1>;
881906
ti,am437x-vpfe-interface = <0>;
882907
bus-width = <8>;
883908
hsync-active = <0>;

‎arch/arm/boot/dts/am43x-epos-evm.dts

Lines changed: 22 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -145,6 +145,12 @@
145145
system-clock-frequency = <12000000>;
146146
};
147147
};
148+
149+
audio_mstrclk: clock {
150+
compatible = "fixed-clock";
151+
#clock-cells = <0>;
152+
clock-frequency = <12000000>;
153+
};
148154
};
149155

150156
&am43xx_pinmux {
@@ -696,6 +702,21 @@
696702
IOVDD-supply = <&dcdc4>; /* V3_3D -> DCDC4 */
697703
DVDD-supply = <&ldo1>; /* V1_8AUD -> V1_8D -> LDO1 */
698704
};
705+
706+
ov2659@30 {
707+
compatible = "ovti,ov2659";
708+
reg = <0x30>;
709+
710+
clocks = <&audio_mstrclk>;
711+
clock-names = "xvclk";
712+
713+
port {
714+
ov2659_1: endpoint {
715+
remote-endpoint = <&vpfe1_ep>;
716+
link-frequencies = /bits/ 64 <70000000>;
717+
};
718+
};
719+
};
699720
};
700721

701722
&i2c2 {
@@ -964,7 +985,7 @@
964985

965986
port {
966987
vpfe1_ep: endpoint {
967-
/* remote-endpoint = <&sensor>; add once we have it */
988+
remote-endpoint = <&ov2659_1>;
968989
ti,am437x-vpfe-interface = <0>;
969990
bus-width = <8>;
970991
hsync-active = <0>;

‎arch/arm/boot/dts/am43xx-clocks.dtsi

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -704,6 +704,60 @@
704704
ti,bit-shift = <8>;
705705
reg = <0x2a48>;
706706
};
707+
708+
clkout1_osc_div_ck: clkout1-osc-div-ck {
709+
#clock-cells = <0>;
710+
compatible = "ti,divider-clock";
711+
clocks = <&sys_clkin_ck>;
712+
ti,bit-shift = <20>;
713+
ti,max-div = <4>;
714+
reg = <0x4100>;
715+
};
716+
717+
clkout1_src2_mux_ck: clkout1-src2-mux-ck {
718+
#clock-cells = <0>;
719+
compatible = "ti,mux-clock";
720+
clocks = <&clk_rc32k_ck>, <&sysclk_div>, <&dpll_ddr_m2_ck>,
721+
<&dpll_per_m2_ck>, <&dpll_disp_m2_ck>,
722+
<&dpll_mpu_m2_ck>;
723+
reg = <0x4100>;
724+
};
725+
726+
clkout1_src2_pre_div_ck: clkout1-src2-pre-div-ck {
727+
#clock-cells = <0>;
728+
compatible = "ti,divider-clock";
729+
clocks = <&clkout1_src2_mux_ck>;
730+
ti,bit-shift = <4>;
731+
ti,max-div = <8>;
732+
reg = <0x4100>;
733+
};
734+
735+
clkout1_src2_post_div_ck: clkout1-src2-post-div-ck {
736+
#clock-cells = <0>;
737+
compatible = "ti,divider-clock";
738+
clocks = <&clkout1_src2_pre_div_ck>;
739+
ti,bit-shift = <8>;
740+
ti,max-div = <32>;
741+
ti,index-power-of-two;
742+
reg = <0x4100>;
743+
};
744+
745+
clkout1_mux_ck: clkout1-mux-ck {
746+
#clock-cells = <0>;
747+
compatible = "ti,mux-clock";
748+
clocks = <&clkout1_osc_div_ck>, <&clk_rc32k_ck>,
749+
<&clkout1_src2_post_div_ck>, <&dpll_extdev_m2_ck>;
750+
ti,bit-shift = <16>;
751+
reg = <0x4100>;
752+
};
753+
754+
clkout1_ck: clkout1-ck {
755+
#clock-cells = <0>;
756+
compatible = "ti,gate-clock";
757+
clocks = <&clkout1_mux_ck>;
758+
ti,bit-shift = <23>;
759+
reg = <0x4100>;
760+
};
707761
};
708762

709763
&prcm {

‎arch/arm/boot/dts/dra7-l4.dtsi

Lines changed: 62 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -4176,35 +4176,88 @@
41764176
};
41774177

41784178
target-module@170000 { /* 0x48970000, ap 21 0a.0 */
4179-
compatible = "ti,sysc";
4180-
status = "disabled";
4179+
compatible = "ti,sysc-omap4", "ti,sysc";
4180+
reg = <0x170010 0x4>;
4181+
reg-names = "sysc";
4182+
ti,sysc-midle = <SYSC_IDLE_FORCE>,
4183+
<SYSC_IDLE_NO>,
4184+
<SYSC_IDLE_SMART>;
4185+
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4186+
<SYSC_IDLE_NO>,
4187+
<SYSC_IDLE_SMART>;
4188+
clocks = <&cam_clkctrl DRA7_CAM_VIP1_CLKCTRL 0>;
4189+
clock-names = "fck";
41814190
#address-cells = <1>;
41824191
#size-cells = <1>;
41834192
ranges = <0x0 0x170000 0x10000>;
4193+
status = "disabled";
41844194
};
41854195

41864196
target-module@190000 { /* 0x48990000, ap 23 2e.0 */
4187-
compatible = "ti,sysc";
4188-
status = "disabled";
4197+
compatible = "ti,sysc-omap4", "ti,sysc";
4198+
reg = <0x190010 0x4>;
4199+
reg-names = "sysc";
4200+
ti,sysc-midle = <SYSC_IDLE_FORCE>,
4201+
<SYSC_IDLE_NO>,
4202+
<SYSC_IDLE_SMART>;
4203+
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4204+
<SYSC_IDLE_NO>,
4205+
<SYSC_IDLE_SMART>;
4206+
clocks = <&cam_clkctrl DRA7_CAM_VIP2_CLKCTRL 0>;
4207+
clock-names = "fck";
41894208
#address-cells = <1>;
41904209
#size-cells = <1>;
41914210
ranges = <0x0 0x190000 0x10000>;
4211+
status = "disabled";
41924212
};
41934213

41944214
target-module@1b0000 { /* 0x489b0000, ap 25 34.0 */
4195-
compatible = "ti,sysc";
4196-
status = "disabled";
4215+
compatible = "ti,sysc-omap4", "ti,sysc";
4216+
reg = <0x1b0000 0x4>,
4217+
<0x1b0010 0x4>;
4218+
reg-names = "rev", "sysc";
4219+
ti,sysc-midle = <SYSC_IDLE_FORCE>,
4220+
<SYSC_IDLE_NO>,
4221+
<SYSC_IDLE_SMART>;
4222+
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4223+
<SYSC_IDLE_NO>,
4224+
<SYSC_IDLE_SMART>;
4225+
clocks = <&cam_clkctrl DRA7_CAM_VIP3_CLKCTRL 0>;
4226+
clock-names = "fck";
41974227
#address-cells = <1>;
41984228
#size-cells = <1>;
41994229
ranges = <0x0 0x1b0000 0x10000>;
4230+
status = "disabled";
42004231
};
42014232

4202-
target-module@1d0000 { /* 0x489d0000, ap 27 30.0 */
4203-
compatible = "ti,sysc";
4204-
status = "disabled";
4233+
target-module@1d0010 { /* 0x489d0000, ap 27 30.0 */
4234+
compatible = "ti,sysc-omap4", "ti,sysc";
4235+
reg = <0x1d0010 0x4>;
4236+
reg-names = "sysc";
4237+
ti,sysc-midle = <SYSC_IDLE_FORCE>,
4238+
<SYSC_IDLE_NO>,
4239+
<SYSC_IDLE_SMART>;
4240+
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
4241+
<SYSC_IDLE_NO>,
4242+
<SYSC_IDLE_SMART>;
4243+
clocks = <&vpe_clkctrl DRA7_VPE_VPE_CLKCTRL 0>;
4244+
clock-names = "fck";
42054245
#address-cells = <1>;
42064246
#size-cells = <1>;
42074247
ranges = <0x0 0x1d0000 0x10000>;
4248+
4249+
vpe: vpe@0 {
4250+
compatible = "ti,dra7-vpe";
4251+
reg = <0x0000 0x120>,
4252+
<0x0700 0x80>,
4253+
<0x5700 0x18>,
4254+
<0xd000 0x400>;
4255+
reg-names = "vpe_top",
4256+
"sc",
4257+
"csc",
4258+
"vpdma";
4259+
interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
4260+
};
42084261
};
42094262
};
42104263
};

‎arch/arm/boot/dts/dra7.dtsi

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -673,6 +673,24 @@
673673
status = "disabled";
674674
};
675675

676+
target-module@56000000 {
677+
compatible = "ti,sysc-omap4", "ti,sysc";
678+
reg = <0x5600fe00 0x4>,
679+
<0x5600fe10 0x4>;
680+
reg-names = "rev", "sysc";
681+
ti,sysc-midle = <SYSC_IDLE_FORCE>,
682+
<SYSC_IDLE_NO>,
683+
<SYSC_IDLE_SMART>;
684+
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
685+
<SYSC_IDLE_NO>,
686+
<SYSC_IDLE_SMART>;
687+
clocks = <&gpu_clkctrl DRA7_GPU_CLKCTRL 0>;
688+
clock-names = "fck";
689+
#address-cells = <1>;
690+
#size-cells = <1>;
691+
ranges = <0 0x56000000 0x2000000>;
692+
};
693+
676694
crossbar_mpu: crossbar@4a002a48 {
677695
compatible = "ti,irq-crossbar";
678696
reg = <0x4a002a48 0x130>;

‎arch/arm/boot/dts/dra72-evm-common.dtsi

Lines changed: 31 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -187,6 +187,12 @@
187187
gpio = <&gpio5 8 GPIO_ACTIVE_HIGH>;
188188
enable-active-high;
189189
};
190+
191+
clk_ov5640_fixed: clock {
192+
compatible = "fixed-clock";
193+
#clock-cells = <0>;
194+
clock-frequency = <24000000>;
195+
};
190196
};
191197

192198
&dra7_pmx_core {
@@ -269,6 +275,23 @@
269275
line-name = "vin6_sel_s0";
270276
};
271277
};
278+
279+
ov5640@3c {
280+
compatible = "ovti,ov5640";
281+
reg = <0x3c>;
282+
283+
clocks = <&clk_ov5640_fixed>;
284+
clock-names = "xclk";
285+
286+
port {
287+
csi2_cam0: endpoint {
288+
remote-endpoint = <&csi2_phy0>;
289+
clock-lanes = <0>;
290+
data-lanes = <1 2>;
291+
};
292+
};
293+
};
294+
272295
};
273296

274297
&uart1 {
@@ -580,3 +603,11 @@
580603
&pcie1_rc {
581604
status = "okay";
582605
};
606+
607+
&csi2_0 {
608+
csi2_phy0: endpoint {
609+
remote-endpoint = <&csi2_cam0>;
610+
clock-lanes = <0>;
611+
data-lanes = <1 2>;
612+
};
613+
};

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