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Merge tag 'phy-for-5.6_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next
Kishon writes: phy: for 5.6 *) Add support in PHY core to create link between PHY consumer and PHY provider *) Add DisplayPort PHY configuration set to be used for negotiating the configurations to be used between DisplayPort controller and DisplayPort PHY *) Add PHY wrapper driver (configure inputs to Cadence Sierra PHY) for TI's J721E SoC and adapt Cadence Sierra PHY driver to be used for J721E SoC (Supports USB and PCIe) *) Add PHY driver for eMMC PHY in Intel LGM SoC *) Add PHY support for 7216 and 7211 Broadcom SoCs which uses the new Synopsys USB Controller *) Add support for 16nm SATA PHY present in Broadcom 7216 SoC *) Fix lost packet issue, fix MDIO from getting inaccessible, fix occasional transaction failures, fix USB driver from crashing in Broadcom USB PHY driver *) Fix missing PCS SW reset in UFS PHY of Qualcomm SM8150 *) Use "struct phy_configure_opts_mipi_dphy" to pass parameters from display controller to rockchip-inno-dsidphy *) Other cleanups including compile testing for some of the PHY drivers, fixing Kconfig indentation, duplicate writes in drivers etc., Signed-off-by: Kishon Vijay Abraham I <[email protected]> * tag 'phy-for-5.6_v2' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy: (54 commits) dt-bindings: phy: Add PHY_TYPE_DP definition phy: ti: j721e-wiz: Fix return value check in wiz_probe() dt-bindings: usb: Convert Allwinner A80 USB PHY controller to a schema phy: intel-lgm-emmc: Fix warning by adding missing MODULE_LICENSE phy: ti: j721e-wiz: Manage typec-gpio-dir dt-bindings: phy: ti,phy-j721e-wiz: Add Type-C dir GPIO phy: cadence: Sierra: add phy_reset hook phy: cadence: Sierra: remove redundant initialization of pointer regmap phy: Add DisplayPort configuration options phy: Enable compile testing for some of drivers phy: mediatek: Fix Kconfig indentation phy: intel-lgm-emmc: Add support for eMMC PHY dt-bindings: phy: intel-emmc-phy: Add YAML schema for LGM eMMC PHY phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC dt-bindings: phy: Document WIZ (SERDES wrapper) bindings phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove() phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz phy: cadence: Sierra: Change MAX_LANES of Sierra to 16 phy: cadence: Sierra: Check for PLL lock during PHY power on phy: cadence: Sierra: Get reset control "array" for each link ...
2 parents 4baa550 + 8a79db5 commit 50f737a

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‎Documentation/devicetree/bindings/phy/allwinner,sun9i-a80-usb-phy.yaml

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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/allwinner,sun9i-a80-usb-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Allwinner A80 USB PHY Device Tree Bindings
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maintainers:
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- Chen-Yu Tsai <[email protected]>
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- Maxime Ripard <[email protected]>
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properties:
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"#phy-cells":
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const: 0
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compatible:
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const: allwinner,sun9i-a80-usb-phy
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reg:
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maxItems: 1
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clocks:
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anyOf:
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- description: Main PHY Clock
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- items:
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- description: Main PHY clock
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- description: HSIC 12MHz clock
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- description: HSIC 480MHz clock
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clock-names:
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oneOf:
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- const: phy
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- items:
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- const: phy
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- const: hsic_12M
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- const: hsic_480M
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resets:
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anyOf:
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- description: Normal USB PHY reset
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- items:
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- description: Normal USB PHY reset
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- description: HSIC Reset
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reset-names:
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oneOf:
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- const: phy
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- items:
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- const: phy
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- const: hsic
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phy_type:
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const: hsic
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description:
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When absent, the PHY type will be assumed to be normal USB.
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phy-supply:
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description:
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Regulator that powers VBUS
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required:
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- "#phy-cells"
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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additionalProperties: false
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if:
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properties:
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phy_type:
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const: hsic
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required:
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- phy_type
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then:
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properties:
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clocks:
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maxItems: 3
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clock-names:
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maxItems: 3
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resets:
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maxItems: 2
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reset-names:
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maxItems: 2
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examples:
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- |
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#include <dt-bindings/clock/sun9i-a80-usb.h>
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#include <dt-bindings/reset/sun9i-a80-usb.h>
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usbphy1: phy@a00800 {
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compatible = "allwinner,sun9i-a80-usb-phy";
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reg = <0x00a00800 0x4>;
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clocks = <&usb_clocks CLK_USB0_PHY>;
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clock-names = "phy";
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resets = <&usb_clocks RST_USB0_PHY>;
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reset-names = "phy";
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phy-supply = <&reg_usb1_vbus>;
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#phy-cells = <0>;
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};
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- |
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#include <dt-bindings/clock/sun9i-a80-usb.h>
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#include <dt-bindings/reset/sun9i-a80-usb.h>
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usbphy3: phy@a02800 {
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compatible = "allwinner,sun9i-a80-usb-phy";
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reg = <0x00a02800 0x4>;
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clocks = <&usb_clocks CLK_USB2_PHY>,
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<&usb_clocks CLK_USB_HSIC>,
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<&usb_clocks CLK_USB2_HSIC>;
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clock-names = "phy",
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"hsic_12M",
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"hsic_480M";
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resets = <&usb_clocks RST_USB2_PHY>,
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<&usb_clocks RST_USB2_HSIC>;
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reset-names = "phy",
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"hsic";
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phy_type = "hsic";
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phy-supply = <&reg_usb3_vbus>;
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#phy-cells = <0>;
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};

‎Documentation/devicetree/bindings/phy/brcm,brcmstb-usb-phy.txt

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Broadcom STB USB PHY
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Required properties:
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- compatible: brcm,brcmstb-usb-phy
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- reg: two offset and length pairs.
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The first pair specifies a manditory set of memory mapped
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registers used for general control of the PHY.
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The second pair specifies optional registers used by some of
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the SoCs that support USB 3.x
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- #phy-cells: Shall be 1 as it expects one argument for setting
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the type of the PHY. Possible values are:
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- PHY_TYPE_USB2 for USB1.1/2.0 PHY
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- PHY_TYPE_USB3 for USB3.x PHY
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- compatible: should be one of
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"brcm,brcmstb-usb-phy"
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"brcm,bcm7216-usb-phy"
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"brcm,bcm7211-usb-phy"
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- reg and reg-names properties requirements are specific to the
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compatible string.
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"brcm,brcmstb-usb-phy":
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- reg: 1 or 2 offset and length pairs. One for the base CTRL registers
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and an optional pair for systems with USB 3.x support
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- reg-names: not specified
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"brcm,bcm7216-usb-phy":
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- reg: 3 offset and length pairs for CTRL, XHCI_EC and XHCI_GBL
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registers
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- reg-names: "ctrl", "xhci_ec", "xhci_gbl"
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"brcm,bcm7211-usb-phy":
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- reg: 5 offset and length pairs for CTRL, XHCI_EC, XHCI_GBL,
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USB_PHY and USB_MDIO registers and an optional pair
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for the BDC registers
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- reg-names: "ctrl", "xhci_ec", "xhci_gbl", "usb_phy", "usb_mdio", "bdc_ec"
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- #phy-cells: Shall be 1 as it expects one argument for setting
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the type of the PHY. Possible values are:
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- PHY_TYPE_USB2 for USB1.1/2.0 PHY
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- PHY_TYPE_USB3 for USB3.x PHY
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Optional Properties:
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- clocks : clock phandles.
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- clock-names: String, clock name.
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- interrupts: wakeup interrupt
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- interrupt-names: "wakeup"
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- brcm,ipp: Boolean, Invert Port Power.
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Possible values are: 0 (Don't invert), 1 (Invert)
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- brcm,ioc: Boolean, Invert Over Current detection.
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Possible values are: 0 (Don't invert), 1 (Invert)
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NOTE: one or both of the following two properties must be set
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- brcm,has-xhci: Boolean indicating the phy has an XHCI phy.
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- brcm,has-eohci: Boolean indicating the phy has an EHCI/OHCI phy.
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- dr_mode: String, PHY Device mode.
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Possible values are: "host", "peripheral ", "drd" or "typec-pd"
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If this property is not defined, the phy will default to "host" mode.
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- brcm,syscon-piarbctl: phandle to syscon for handling config registers
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NOTE: one or both of the following two properties must be set
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- brcm,has-xhci: Boolean indicating the phy has an XHCI phy.
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- brcm,has-eohci: Boolean indicating the phy has an EHCI/OHCI phy.
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Example:
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@@ -41,3 +60,27 @@ usbphy_0: usb-phy@f0470200 {
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clocks = <&usb20>, <&usb30>;
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clock-names = "sw_usb", "sw_usb3";
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};
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usb-phy@29f0200 {
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reg = <0x29f0200 0x200>,
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<0x29c0880 0x30>,
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<0x29cc100 0x534>,
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<0x2808000 0x24>,
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<0x2980080 0x8>;
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reg-names = "ctrl",
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"xhci_ec",
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"xhci_gbl",
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"usb_phy",
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"usb_mdio";
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brcm,ioc = <0x0>;
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brcm,ipp = <0x0>;
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compatible = "brcm,bcm7211-usb-phy";
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interrupts = <0x30>;
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interrupt-parent = <&vpu_intr1_nosec_intc>;
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interrupt-names = "wake";
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#phy-cells = <0x1>;
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brcm,has-xhci;
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syscon-piarbctl = <&syscon_piarbctl>;
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clocks = <&scmi_clk 256>;
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clock-names = "sw_usb";
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};

‎Documentation/devicetree/bindings/phy/brcm-sata-phy.txt

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Required properties:
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- compatible: should be one or more of
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"brcm,bcm7216-sata-phy"
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"brcm,bcm7425-sata-phy"
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"brcm,bcm7445-sata-phy"
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"brcm,iproc-ns2-sata-phy"

‎Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml

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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Intel Lightning Mountain(LGM) eMMC PHY Device Tree Bindings
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maintainers:
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- Ramuthevar Vadivel Murugan <[email protected]>
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description: |+
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Bindings for eMMC PHY on Intel's Lightning Mountain SoC, syscon
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node is used to reference the base address of eMMC phy registers.
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The eMMC PHY node should be the child of a syscon node with the
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required property:
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- compatible: Should be one of the following:
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"intel,lgm-syscon", "syscon"
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- reg:
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maxItems: 1
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properties:
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compatible:
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const: intel,lgm-emmc-phy
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"#phy-cells":
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const: 0
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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required:
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- "#phy-cells"
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- compatible
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- reg
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- clocks
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examples:
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- |
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sysconf: chiptop@e0200000 {
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compatible = "intel,lgm-syscon", "syscon";
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reg = <0xe0200000 0x100>;
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emmc-phy: emmc-phy@a8 {
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compatible = "intel,lgm-emmc-phy";
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reg = <0x00a8 0x10>;
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clocks = <&emmc>;
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#phy-cells = <0>;
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};
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};
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...

‎Documentation/devicetree/bindings/phy/phy-cadence-sierra.txt

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-----------------------
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Required properties:
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- compatible: cdns,sierra-phy-t0
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- clocks: Must contain an entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must be "phy_clk"
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- compatible: Must be "cdns,sierra-phy-t0" for Sierra in Cadence platform
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Must be "ti,sierra-phy-t0" for Sierra in TI's J721E SoC.
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- resets: Must contain an entry for each in reset-names.
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See ../reset/reset.txt for details.
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- reset-names: Must include "sierra_reset" and "sierra_apb".
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"sierra_reset" must control the reset line to the PHY.
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"sierra_apb" must control the reset line to the APB PHY
14-
interface.
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interface ("sierra_apb" is optional).
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- reg: register range for the PHY.
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- #address-cells: Must be 1
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- #size-cells: Must be 0
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Optional properties:
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- clocks: Must contain an entry in clock-names.
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See ../clocks/clock-bindings.txt for details.
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- clock-names: Must contain "cmn_refclk_dig_div" and
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"cmn_refclk1_dig_div" for configuring the frequency of
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the clock to the lanes. "phy_clk" is deprecated.
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- cdns,autoconf: A boolean property whose presence indicates that the
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PHY registers will be configured by hardware. If not
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present, all sub-node optional properties must be

‎Documentation/devicetree/bindings/phy/rockchip,px30-dsi-dphy.yaml

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"#phy-cells":
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const: 0
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"#clock-cells":
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const: 0
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compatible:
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enum:
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- rockchip,px30-dsi-dphy
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required:
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- "#phy-cells"
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- "#clock-cells"
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- compatible
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- reg
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- clocks
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reg = <0x0 0xff2e0000 0x0 0x10000>;
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clocks = <&pmucru 13>, <&cru 12>;
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clock-names = "ref", "pclk";
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#clock-cells = <0>;
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resets = <&cru 12>;
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reset-names = "apb";
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#phy-cells = <0>;

‎Documentation/devicetree/bindings/phy/sun9i-usb-phy.txt

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This file was deleted.

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