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xdarklightsuperna9999
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arm64: dts: amlogic: gx: fix reference to unknown/untested PWM clock
Device-tree expects absent clocks to be specified as <0> (instead of using <>). This fixes using the FCLK4/FCLK3 clocks as they are now seen at their correct index (while before they were recognized, but at the correct index - resulting in the hardware using a different clock than what the kernel sees). Fixes: a526eee ("arm64: dts: amlogic: gx: switch to the new PWM controller binding") Signed-off-by: Martin Blumenstingl <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Neil Armstrong <[email protected]>
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arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -741,7 +741,7 @@
741741

742742
&pwm_ab {
743743
clocks = <&xtal>,
744-
<>, /* unknown/untested, the datasheet calls it "vid_pll" */
744+
<0>, /* unknown/untested, the datasheet calls it "vid_pll" */
745745
<&clkc CLKID_FCLK_DIV4>,
746746
<&clkc CLKID_FCLK_DIV3>;
747747
};
@@ -752,14 +752,14 @@
752752

753753
&pwm_cd {
754754
clocks = <&xtal>,
755-
<>, /* unknown/untested, the datasheet calls it "vid_pll" */
755+
<0>, /* unknown/untested, the datasheet calls it "vid_pll" */
756756
<&clkc CLKID_FCLK_DIV4>,
757757
<&clkc CLKID_FCLK_DIV3>;
758758
};
759759

760760
&pwm_ef {
761761
clocks = <&xtal>,
762-
<>, /* unknown/untested, the datasheet calls it "vid_pll" */
762+
<0>, /* unknown/untested, the datasheet calls it "vid_pll" */
763763
<&clkc CLKID_FCLK_DIV4>,
764764
<&clkc CLKID_FCLK_DIV3>;
765765
};

arch/arm64/boot/dts/amlogic/meson-gxl.dtsi

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -811,7 +811,7 @@
811811

812812
&pwm_ab {
813813
clocks = <&xtal>,
814-
<>, /* unknown/untested, the datasheet calls it "vid_pll" */
814+
<0>, /* unknown/untested, the datasheet calls it "vid_pll" */
815815
<&clkc CLKID_FCLK_DIV4>,
816816
<&clkc CLKID_FCLK_DIV3>;
817817
};
@@ -822,14 +822,14 @@
822822

823823
&pwm_cd {
824824
clocks = <&xtal>,
825-
<>, /* unknown/untested, the datasheet calls it "vid_pll" */
825+
<0>, /* unknown/untested, the datasheet calls it "vid_pll" */
826826
<&clkc CLKID_FCLK_DIV4>,
827827
<&clkc CLKID_FCLK_DIV3>;
828828
};
829829

830830
&pwm_ef {
831831
clocks = <&xtal>,
832-
<>, /* unknown/untested, the datasheet calls it "vid_pll" */
832+
<0>, /* unknown/untested, the datasheet calls it "vid_pll" */
833833
<&clkc CLKID_FCLK_DIV4>,
834834
<&clkc CLKID_FCLK_DIV3>;
835835
};

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