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30 | 30 | #define CTRL_IO_DUAL_DATA BIT(29)
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31 | 31 | #define CTRL_IO_QUAD_DATA BIT(30)
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32 | 32 | #define CTRL_COMMAND_SHIFT 16
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| 33 | +#define CTRL_IO_ADDRESS_4B BIT(13) /* AST2400 SPI only */ |
33 | 34 | #define CTRL_IO_DUMMY_SET(dummy) \
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34 | 35 | (((((dummy) >> 2) & 0x1) << 14) | (((dummy) & 0x3) << 6))
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35 | 36 | #define CTRL_CE_STOP_ACTIVE BIT(2)
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@@ -280,6 +281,8 @@ static bool aspeed_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op
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280 | 281 | return spi_mem_default_supports_op(mem, op);
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281 | 282 | }
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282 | 283 |
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| 284 | +static const struct aspeed_spi_data ast2400_spi_data; |
| 285 | + |
283 | 286 | static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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284 | 287 | {
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285 | 288 | struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
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@@ -309,6 +312,9 @@ static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *o
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309 | 312 | addr_mode |= (0x11 << chip->cs);
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310 | 313 | else
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311 | 314 | addr_mode &= ~(0x11 << chip->cs);
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| 315 | + |
| 316 | + if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data) |
| 317 | + ctl_val |= CTRL_IO_ADDRESS_4B; |
312 | 318 | }
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313 | 319 |
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314 | 320 | if (op->dummy.nbytes)
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@@ -398,7 +404,13 @@ static int aspeed_spi_chip_set_default_window(struct aspeed_spi_chip *chip)
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398 | 404 | struct aspeed_spi_window windows[ASPEED_SPI_MAX_NUM_CS] = { 0 };
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399 | 405 | struct aspeed_spi_window *win = &windows[chip->cs];
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400 | 406 |
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401 |
| - aspeed_spi_get_windows(aspi, windows); |
| 407 | + /* No segment registers for the AST2400 SPI controller */ |
| 408 | + if (aspi->data == &ast2400_spi_data) { |
| 409 | + win->offset = 0; |
| 410 | + win->size = aspi->ahb_window_size; |
| 411 | + } else { |
| 412 | + aspeed_spi_get_windows(aspi, windows); |
| 413 | + } |
402 | 414 |
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403 | 415 | chip->ahb_base = aspi->ahb_base + win->offset;
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404 | 416 | chip->ahb_window_size = win->size;
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@@ -461,6 +473,10 @@ static int aspeed_spi_chip_adjust_window(struct aspeed_spi_chip *chip,
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461 | 473 | struct aspeed_spi_window *win = &windows[chip->cs];
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462 | 474 | int ret;
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463 | 475 |
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| 476 | + /* No segment registers for the AST2400 SPI controller */ |
| 477 | + if (aspi->data == &ast2400_spi_data) |
| 478 | + return 0; |
| 479 | + |
464 | 480 | /*
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465 | 481 | * Due to an HW issue on the AST2500 SPI controller, the CE0
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466 | 482 | * window size should be smaller than the maximum 128MB.
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@@ -545,6 +561,12 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
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545 | 561 | else
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546 | 562 | addr_mode &= ~(0x11 << chip->cs);
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547 | 563 | writel(addr_mode, aspi->regs + CE_CTRL_REG);
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| 564 | + |
| 565 | + /* AST2400 SPI controller sets 4BYTE address mode in |
| 566 | + * CE0 Control Register |
| 567 | + */ |
| 568 | + if (op->addr.nbytes == 4 && chip->aspi->data == &ast2400_spi_data) |
| 569 | + ctl_val |= CTRL_IO_ADDRESS_4B; |
548 | 570 | }
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549 | 571 |
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550 | 572 | /* READ mode is the controller default setting */
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@@ -816,6 +838,14 @@ static const struct aspeed_spi_data ast2400_fmc_data = {
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816 | 838 | .segment_reg = aspeed_spi_segment_reg,
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817 | 839 | };
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818 | 840 |
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| 841 | +static const struct aspeed_spi_data ast2400_spi_data = { |
| 842 | + .max_cs = 1, |
| 843 | + .hastype = false, |
| 844 | + .we0 = 0, |
| 845 | + .ctl0 = 0x04, |
| 846 | + /* No segment registers */ |
| 847 | +}; |
| 848 | + |
819 | 849 | static const struct aspeed_spi_data ast2500_fmc_data = {
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820 | 850 | .max_cs = 3,
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821 | 851 | .hastype = true,
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@@ -860,6 +890,7 @@ static const struct aspeed_spi_data ast2600_spi_data = {
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860 | 890 |
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861 | 891 | static const struct of_device_id aspeed_spi_matches[] = {
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862 | 892 | { .compatible = "aspeed,ast2400-fmc", .data = &ast2400_fmc_data },
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| 893 | + { .compatible = "aspeed,ast2400-spi", .data = &ast2400_spi_data }, |
863 | 894 | { .compatible = "aspeed,ast2500-fmc", .data = &ast2500_fmc_data },
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864 | 895 | { .compatible = "aspeed,ast2500-spi", .data = &ast2500_spi_data },
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865 | 896 | { .compatible = "aspeed,ast2600-fmc", .data = &ast2600_fmc_data },
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