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Commit 5390130

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Tero Kristotmlind
Tero Kristo
authored and
tmlind
committed
ARM: dts: dra7: add timer_sys_ck entries for IPU/DSP timers
With this, the clocksource driver can setup the timers properly. Signed-off-by: Tero Kristo <[email protected]> Signed-off-by: Tony Lindgren <[email protected]>
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+26
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‎arch/arm/boot/dts/dra7-l4.dtsi

Lines changed: 26 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1163,8 +1163,8 @@
11631163
timer2: timer@0 {
11641164
compatible = "ti,omap5430-timer";
11651165
reg = <0x0 0x80>;
1166-
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>;
1167-
clock-names = "fck";
1166+
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER2_CLKCTRL 24>, <&timer_sys_clk_div>;
1167+
clock-names = "fck", "timer_sys_ck";
11681168
interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
11691169
};
11701170
};
@@ -1191,8 +1191,8 @@
11911191
timer3: timer@0 {
11921192
compatible = "ti,omap5430-timer";
11931193
reg = <0x0 0x80>;
1194-
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>;
1195-
clock-names = "fck";
1194+
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER3_CLKCTRL 24>, <&timer_sys_clk_div>;
1195+
clock-names = "fck", "timer_sys_ck";
11961196
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
11971197
};
11981198
};
@@ -1210,17 +1210,18 @@
12101210
<SYSC_IDLE_SMART>,
12111211
<SYSC_IDLE_SMART_WKUP>;
12121212
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1213-
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>;
1214-
clock-names = "fck";
1213+
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>,
1214+
<&timer_sys_clk_div>;
1215+
clock-names = "fck", "timer_sys_ck";
12151216
#address-cells = <1>;
12161217
#size-cells = <1>;
12171218
ranges = <0x0 0x36000 0x1000>;
12181219

12191220
timer4: timer@0 {
12201221
compatible = "ti,omap5430-timer";
12211222
reg = <0x0 0x80>;
1222-
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>;
1223-
clock-names = "fck";
1223+
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 24>, <&timer_sys_clk_div>;
1224+
clock-names = "fck", "timer_sys_ck";
12241225
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
12251226
};
12261227
};
@@ -1246,8 +1247,8 @@
12461247
timer9: timer@0 {
12471248
compatible = "ti,omap5430-timer";
12481249
reg = <0x0 0x80>;
1249-
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>;
1250-
clock-names = "fck";
1250+
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER9_CLKCTRL 24>, <&timer_sys_clk_div>;
1251+
clock-names = "fck", "timer_sys_ck";
12511252
interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
12521253
};
12531254
};
@@ -1853,8 +1854,8 @@
18531854
timer10: timer@0 {
18541855
compatible = "ti,omap5430-timer";
18551856
reg = <0x0 0x80>;
1856-
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>;
1857-
clock-names = "fck";
1857+
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER10_CLKCTRL 24>, <&timer_sys_clk_div>;
1858+
clock-names = "fck", "timer_sys_ck";
18581859
interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
18591860
};
18601861
};
@@ -1880,8 +1881,8 @@
18801881
timer11: timer@0 {
18811882
compatible = "ti,omap5430-timer";
18821883
reg = <0x0 0x80>;
1883-
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>;
1884-
clock-names = "fck";
1884+
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER11_CLKCTRL 24>, <&timer_sys_clk_div>;
1885+
clock-names = "fck", "timer_sys_ck";
18851886
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
18861887
};
18871888
};
@@ -3354,8 +3355,8 @@
33543355
<SYSC_IDLE_SMART>,
33553356
<SYSC_IDLE_SMART_WKUP>;
33563357
/* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3357-
clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>;
3358-
clock-names = "fck";
3358+
clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>, <&timer_sys_clk_div>;
3359+
clock-names = "fck", "timer_sys_ck";
33593360
#address-cells = <1>;
33603361
#size-cells = <1>;
33613362
ranges = <0x0 0x20000 0x1000>;
@@ -3381,8 +3382,9 @@
33813382
<SYSC_IDLE_SMART>,
33823383
<SYSC_IDLE_SMART_WKUP>;
33833384
/* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3384-
clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>;
3385-
clock-names = "fck";
3385+
clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>,
3386+
<&timer_sys_clk_div>;
3387+
clock-names = "fck", "timer_sys_ck";
33863388
#address-cells = <1>;
33873389
#size-cells = <1>;
33883390
ranges = <0x0 0x22000 0x1000>;
@@ -3417,8 +3419,8 @@
34173419
timer7: timer@0 {
34183420
compatible = "ti,omap5430-timer";
34193421
reg = <0x0 0x80>;
3420-
clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>;
3421-
clock-names = "fck";
3422+
clocks = <&ipu_clkctrl DRA7_IPU_TIMER7_CLKCTRL 24>, <&timer_sys_clk_div>;
3423+
clock-names = "fck", "timer_sys_ck";
34223424
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
34233425
};
34243426
};
@@ -3444,8 +3446,8 @@
34443446
timer8: timer@0 {
34453447
compatible = "ti,omap5430-timer";
34463448
reg = <0x0 0x80>;
3447-
clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>;
3448-
clock-names = "fck";
3449+
clocks = <&ipu_clkctrl DRA7_IPU_TIMER8_CLKCTRL 24>, <&timer_sys_clk_div>;
3450+
clock-names = "fck", "timer_sys_ck";
34493451
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
34503452
};
34513453
};
@@ -3471,8 +3473,8 @@
34713473
timer13: timer@0 {
34723474
compatible = "ti,omap5430-timer";
34733475
reg = <0x0 0x80>;
3474-
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>;
3475-
clock-names = "fck";
3476+
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER13_CLKCTRL 24>, <&timer_sys_clk_div>;
3477+
clock-names = "fck", "timer_sys_ck";
34763478
interrupts = <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>;
34773479
ti,timer-pwm;
34783480
};

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