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Merge branches 'clk-actions', 'clk-rockchip', 'clk-iproc', 'clk-intel' and 'clk-debugfs' into clk-next
- RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs * clk-actions: MAINTAINERS: Add reset binding entry for Actions Semi Owl SoCs clk: actions: Add Actions S500 SoC Reset Management Unit support dt-bindings: reset: Add binding constants for Actions S500 RMU clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoC dt-bindings: clock: Add APB, DMAC, GPIO bindings for Actions S500 SoC clk: actions: Fix h_clk for Actions S500 SoC * clk-rockchip: clk: rockchip: add sclk_mac_lbtest to rk3188_critical_clocks clk: rockchip: Revert "fix wrong mmc sample phase shift for rk3328" clk: rockchip: use separate compatibles for rk3288w-cru dt-bindings: clocks: add rk3288w variant compatible clk: rockchip: Handle clock tree for rk3288w variant clk: rockchip: convert rk3036 pll type to use internal lock status clk: rockchip: convert basic pll lock_wait to use regmap_read_poll_timeout clk: rockchip: convert rk3399 pll type to use readl_relaxed_poll_timeout * clk-iproc: clk: iproc: round clock rate to the closest * clk-intel: clk: intel: Avoid unnecessary memset by improving code clk: intel: Improve locking in the driver clk: intel: Use devm_clk_hw_register() instead of clk_hw_register() * clk-debugfs: clk: Add support for enabling/disabling clocks from debugfs
6 parents 987106e + cb7c667 + aab58ac + 9f7d504 + d310124 + 03111b1 commit 53e0742

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13 files changed

+295
-62
lines changed

13 files changed

+295
-62
lines changed

Documentation/devicetree/bindings/clock/rockchip,rk3288-cru.txt

Lines changed: 7 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,9 +4,15 @@ The RK3288 clock controller generates and supplies clock to various
44
controllers within the SoC and also implements a reset controller for SoC
55
peripherals.
66

7+
A revision of this SoC is available: rk3288w. The clock tree is a bit
8+
different so another dt-compatible is available. Noticed that it is only
9+
setting the difference but there is no automatic revision detection. This
10+
should be performed by bootloaders.
11+
712
Required Properties:
813

9-
- compatible: should be "rockchip,rk3288-cru"
14+
- compatible: should be "rockchip,rk3288-cru" or "rockchip,rk3288w-cru" in
15+
case of this revision of Rockchip rk3288.
1016
- reg: physical base address of the controller and length of memory mapped
1117
region.
1218
- #clock-cells: should be 1.

MAINTAINERS

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1533,6 +1533,7 @@ F: drivers/mmc/host/owl-mmc.c
15331533
F: drivers/pinctrl/actions/*
15341534
F: drivers/soc/actions/
15351535
F: include/dt-bindings/power/owl-*
1536+
F: include/dt-bindings/reset/actions,*
15361537
F: include/linux/soc/actions/
15371538
N: owl
15381539

drivers/clk/actions/owl-s500.c

Lines changed: 88 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -23,8 +23,10 @@
2323
#include "owl-gate.h"
2424
#include "owl-mux.h"
2525
#include "owl-pll.h"
26+
#include "owl-reset.h"
2627

2728
#include <dt-bindings/clock/actions,s500-cmu.h>
29+
#include <dt-bindings/reset/actions,s500-reset.h>
2830

2931
#define CMU_COREPLL (0x0000)
3032
#define CMU_DEVPLL (0x0004)
@@ -175,6 +177,8 @@ static OWL_MUX(dev_clk, "dev_clk", dev_clk_mux_p, CMU_DEVPLL, 12, 1, CLK_SET_RAT
175177
static OWL_MUX(ahbprediv_clk, "ahbprediv_clk", ahbprediv_clk_mux_p, CMU_BUSCLK1, 8, 3, CLK_SET_RATE_PARENT);
176178

177179
/* gate clocks */
180+
static OWL_GATE(gpio_clk, "gpio_clk", "apb_clk", CMU_DEVCLKEN0, 18, 0, 0);
181+
static OWL_GATE(dmac_clk, "dmac_clk", "h_clk", CMU_DEVCLKEN0, 1, 0, 0);
178182
static OWL_GATE(spi0_clk, "spi0_clk", "ahb_clk", CMU_DEVCLKEN1, 10, 0, CLK_IGNORE_UNUSED);
179183
static OWL_GATE(spi1_clk, "spi1_clk", "ahb_clk", CMU_DEVCLKEN1, 11, 0, CLK_IGNORE_UNUSED);
180184
static OWL_GATE(spi2_clk, "spi2_clk", "ahb_clk", CMU_DEVCLKEN1, 12, 0, CLK_IGNORE_UNUSED);
@@ -183,7 +187,8 @@ static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
183187
static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
184188

185189
/* divider clocks */
186-
static OWL_DIVIDER(h_clk, "h_clk", "ahbprevdiv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
190+
static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
191+
static OWL_DIVIDER(apb_clk, "apb_clk", "ahb_clk", CMU_BUSCLK1, 14, 2, NULL, 0, 0);
187192
static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
188193

189194
/* factor clocks */
@@ -428,6 +433,9 @@ static struct owl_clk_common *s500_clks[] = {
428433
&spdif_clk.common,
429434
&nand_clk.common,
430435
&ecc_clk.common,
436+
&apb_clk.common,
437+
&dmac_clk.common,
438+
&gpio_clk.common,
431439
};
432440

433441
static struct clk_hw_onecell_data s500_hw_clks = {
@@ -484,24 +492,103 @@ static struct clk_hw_onecell_data s500_hw_clks = {
484492
[CLK_SPDIF] = &spdif_clk.common.hw,
485493
[CLK_NAND] = &nand_clk.common.hw,
486494
[CLK_ECC] = &ecc_clk.common.hw,
495+
[CLK_APB] = &apb_clk.common.hw,
496+
[CLK_DMAC] = &dmac_clk.common.hw,
497+
[CLK_GPIO] = &gpio_clk.common.hw,
487498
},
488499
.num = CLK_NR_CLKS,
489500
};
490501

502+
static const struct owl_reset_map s500_resets[] = {
503+
[RESET_DMAC] = { CMU_DEVRST0, BIT(0) },
504+
[RESET_NORIF] = { CMU_DEVRST0, BIT(1) },
505+
[RESET_DDR] = { CMU_DEVRST0, BIT(2) },
506+
[RESET_NANDC] = { CMU_DEVRST0, BIT(3) },
507+
[RESET_SD0] = { CMU_DEVRST0, BIT(4) },
508+
[RESET_SD1] = { CMU_DEVRST0, BIT(5) },
509+
[RESET_PCM1] = { CMU_DEVRST0, BIT(6) },
510+
[RESET_DE] = { CMU_DEVRST0, BIT(7) },
511+
[RESET_LCD] = { CMU_DEVRST0, BIT(8) },
512+
[RESET_SD2] = { CMU_DEVRST0, BIT(9) },
513+
[RESET_DSI] = { CMU_DEVRST0, BIT(10) },
514+
[RESET_CSI] = { CMU_DEVRST0, BIT(11) },
515+
[RESET_BISP] = { CMU_DEVRST0, BIT(12) },
516+
[RESET_KEY] = { CMU_DEVRST0, BIT(14) },
517+
[RESET_GPIO] = { CMU_DEVRST0, BIT(15) },
518+
[RESET_AUDIO] = { CMU_DEVRST0, BIT(17) },
519+
[RESET_PCM0] = { CMU_DEVRST0, BIT(18) },
520+
[RESET_VDE] = { CMU_DEVRST0, BIT(19) },
521+
[RESET_VCE] = { CMU_DEVRST0, BIT(20) },
522+
[RESET_GPU3D] = { CMU_DEVRST0, BIT(22) },
523+
[RESET_NIC301] = { CMU_DEVRST0, BIT(23) },
524+
[RESET_LENS] = { CMU_DEVRST0, BIT(26) },
525+
[RESET_PERIPHRESET] = { CMU_DEVRST0, BIT(27) },
526+
[RESET_USB2_0] = { CMU_DEVRST1, BIT(0) },
527+
[RESET_TVOUT] = { CMU_DEVRST1, BIT(1) },
528+
[RESET_HDMI] = { CMU_DEVRST1, BIT(2) },
529+
[RESET_HDCP2TX] = { CMU_DEVRST1, BIT(3) },
530+
[RESET_UART6] = { CMU_DEVRST1, BIT(4) },
531+
[RESET_UART0] = { CMU_DEVRST1, BIT(5) },
532+
[RESET_UART1] = { CMU_DEVRST1, BIT(6) },
533+
[RESET_UART2] = { CMU_DEVRST1, BIT(7) },
534+
[RESET_SPI0] = { CMU_DEVRST1, BIT(8) },
535+
[RESET_SPI1] = { CMU_DEVRST1, BIT(9) },
536+
[RESET_SPI2] = { CMU_DEVRST1, BIT(10) },
537+
[RESET_SPI3] = { CMU_DEVRST1, BIT(11) },
538+
[RESET_I2C0] = { CMU_DEVRST1, BIT(12) },
539+
[RESET_I2C1] = { CMU_DEVRST1, BIT(13) },
540+
[RESET_USB3] = { CMU_DEVRST1, BIT(14) },
541+
[RESET_UART3] = { CMU_DEVRST1, BIT(15) },
542+
[RESET_UART4] = { CMU_DEVRST1, BIT(16) },
543+
[RESET_UART5] = { CMU_DEVRST1, BIT(17) },
544+
[RESET_I2C2] = { CMU_DEVRST1, BIT(18) },
545+
[RESET_I2C3] = { CMU_DEVRST1, BIT(19) },
546+
[RESET_ETHERNET] = { CMU_DEVRST1, BIT(20) },
547+
[RESET_CHIPID] = { CMU_DEVRST1, BIT(21) },
548+
[RESET_USB2_1] = { CMU_DEVRST1, BIT(22) },
549+
[RESET_WD0RESET] = { CMU_DEVRST1, BIT(24) },
550+
[RESET_WD1RESET] = { CMU_DEVRST1, BIT(25) },
551+
[RESET_WD2RESET] = { CMU_DEVRST1, BIT(26) },
552+
[RESET_WD3RESET] = { CMU_DEVRST1, BIT(27) },
553+
[RESET_DBG0RESET] = { CMU_DEVRST1, BIT(28) },
554+
[RESET_DBG1RESET] = { CMU_DEVRST1, BIT(29) },
555+
[RESET_DBG2RESET] = { CMU_DEVRST1, BIT(30) },
556+
[RESET_DBG3RESET] = { CMU_DEVRST1, BIT(31) },
557+
};
558+
491559
static struct owl_clk_desc s500_clk_desc = {
492560
.clks = s500_clks,
493561
.num_clks = ARRAY_SIZE(s500_clks),
494562

495563
.hw_clks = &s500_hw_clks,
564+
565+
.resets = s500_resets,
566+
.num_resets = ARRAY_SIZE(s500_resets),
496567
};
497568

498569
static int s500_clk_probe(struct platform_device *pdev)
499570
{
500571
struct owl_clk_desc *desc;
572+
struct owl_reset *reset;
573+
int ret;
501574

502575
desc = &s500_clk_desc;
503576
owl_clk_regmap_init(pdev, desc);
504577

578+
reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
579+
if (!reset)
580+
return -ENOMEM;
581+
582+
reset->rcdev.of_node = pdev->dev.of_node;
583+
reset->rcdev.ops = &owl_reset_ops;
584+
reset->rcdev.nr_resets = desc->num_resets;
585+
reset->reset_map = desc->resets;
586+
reset->regmap = desc->regmap;
587+
588+
ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev);
589+
if (ret)
590+
dev_err(&pdev->dev, "Failed to register reset controller\n");
591+
505592
return owl_clk_probe(&pdev->dev, desc->hw_clks);
506593
}
507594

drivers/clk/bcm/clk-iproc-asiu.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -119,7 +119,7 @@ static long iproc_asiu_clk_round_rate(struct clk_hw *hw, unsigned long rate,
119119
if (rate == *parent_rate)
120120
return *parent_rate;
121121

122-
div = DIV_ROUND_UP(*parent_rate, rate);
122+
div = DIV_ROUND_CLOSEST(*parent_rate, rate);
123123
if (div < 2)
124124
return *parent_rate;
125125

@@ -145,7 +145,7 @@ static int iproc_asiu_clk_set_rate(struct clk_hw *hw, unsigned long rate,
145145
return 0;
146146
}
147147

148-
div = DIV_ROUND_UP(parent_rate, rate);
148+
div = DIV_ROUND_CLOSEST(parent_rate, rate);
149149
if (div < 2)
150150
return -EINVAL;
151151

drivers/clk/clk.c

Lines changed: 29 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3054,6 +3054,31 @@ static int clk_rate_set(void *data, u64 val)
30543054
}
30553055

30563056
#define clk_rate_mode 0644
3057+
3058+
static int clk_prepare_enable_set(void *data, u64 val)
3059+
{
3060+
struct clk_core *core = data;
3061+
int ret = 0;
3062+
3063+
if (val)
3064+
ret = clk_prepare_enable(core->hw->clk);
3065+
else
3066+
clk_disable_unprepare(core->hw->clk);
3067+
3068+
return ret;
3069+
}
3070+
3071+
static int clk_prepare_enable_get(void *data, u64 *val)
3072+
{
3073+
struct clk_core *core = data;
3074+
3075+
*val = core->enable_count && core->prepare_count;
3076+
return 0;
3077+
}
3078+
3079+
DEFINE_DEBUGFS_ATTRIBUTE(clk_prepare_enable_fops, clk_prepare_enable_get,
3080+
clk_prepare_enable_set, "%llu\n");
3081+
30573082
#else
30583083
#define clk_rate_set NULL
30593084
#define clk_rate_mode 0444
@@ -3231,6 +3256,10 @@ static void clk_debug_create_one(struct clk_core *core, struct dentry *pdentry)
32313256
debugfs_create_u32("clk_notifier_count", 0444, root, &core->notifier_count);
32323257
debugfs_create_file("clk_duty_cycle", 0444, root, core,
32333258
&clk_duty_cycle_fops);
3259+
#ifdef CLOCK_ALLOW_WRITE_DEBUGFS
3260+
debugfs_create_file("clk_prepare_enable", 0644, root, core,
3261+
&clk_prepare_enable_fops);
3262+
#endif
32343263

32353264
if (core->num_parents > 0)
32363265
debugfs_create_file("clk_parent", 0444, root, core,

drivers/clk/rockchip/clk-pll.c

Lines changed: 41 additions & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,7 @@
1212
#include <linux/io.h>
1313
#include <linux/delay.h>
1414
#include <linux/clk-provider.h>
15+
#include <linux/iopoll.h>
1516
#include <linux/regmap.h>
1617
#include <linux/clk.h>
1718
#include "clk.h"
@@ -86,23 +87,14 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
8687
{
8788
struct regmap *grf = pll->ctx->grf;
8889
unsigned int val;
89-
int delay = 24000000, ret;
90-
91-
while (delay > 0) {
92-
ret = regmap_read(grf, pll->lock_offset, &val);
93-
if (ret) {
94-
pr_err("%s: failed to read pll lock status: %d\n",
95-
__func__, ret);
96-
return ret;
97-
}
90+
int ret;
9891

99-
if (val & BIT(pll->lock_shift))
100-
return 0;
101-
delay--;
102-
}
92+
ret = regmap_read_poll_timeout(grf, pll->lock_offset, val,
93+
val & BIT(pll->lock_shift), 0, 1000);
94+
if (ret)
95+
pr_err("%s: timeout waiting for pll to lock\n", __func__);
10396

104-
pr_err("%s: timeout waiting for pll to lock\n", __func__);
105-
return -ETIMEDOUT;
97+
return ret;
10698
}
10799

108100
/**
@@ -118,12 +110,31 @@ static int rockchip_pll_wait_lock(struct rockchip_clk_pll *pll)
118110
#define RK3036_PLLCON1_REFDIV_SHIFT 0
119111
#define RK3036_PLLCON1_POSTDIV2_MASK 0x7
120112
#define RK3036_PLLCON1_POSTDIV2_SHIFT 6
113+
#define RK3036_PLLCON1_LOCK_STATUS BIT(10)
121114
#define RK3036_PLLCON1_DSMPD_MASK 0x1
122115
#define RK3036_PLLCON1_DSMPD_SHIFT 12
116+
#define RK3036_PLLCON1_PWRDOWN BIT(13)
123117
#define RK3036_PLLCON2_FRAC_MASK 0xffffff
124118
#define RK3036_PLLCON2_FRAC_SHIFT 0
125119

126-
#define RK3036_PLLCON1_PWRDOWN (1 << 13)
120+
static int rockchip_rk3036_pll_wait_lock(struct rockchip_clk_pll *pll)
121+
{
122+
u32 pllcon;
123+
int ret;
124+
125+
/*
126+
* Lock time typical 250, max 500 input clock cycles @24MHz
127+
* So define a very safe maximum of 1000us, meaning 24000 cycles.
128+
*/
129+
ret = readl_relaxed_poll_timeout(pll->reg_base + RK3036_PLLCON(1),
130+
pllcon,
131+
pllcon & RK3036_PLLCON1_LOCK_STATUS,
132+
0, 1000);
133+
if (ret)
134+
pr_err("%s: timeout waiting for pll to lock\n", __func__);
135+
136+
return ret;
137+
}
127138

128139
static void rockchip_rk3036_pll_get_params(struct rockchip_clk_pll *pll,
129140
struct rockchip_pll_rate_table *rate)
@@ -221,7 +232,7 @@ static int rockchip_rk3036_pll_set_params(struct rockchip_clk_pll *pll,
221232
writel_relaxed(pllcon, pll->reg_base + RK3036_PLLCON(2));
222233

223234
/* wait for the pll to lock */
224-
ret = rockchip_pll_wait_lock(pll);
235+
ret = rockchip_rk3036_pll_wait_lock(pll);
225236
if (ret) {
226237
pr_warn("%s: pll update unsuccessful, trying to restore old params\n",
227238
__func__);
@@ -260,7 +271,7 @@ static int rockchip_rk3036_pll_enable(struct clk_hw *hw)
260271

261272
writel(HIWORD_UPDATE(0, RK3036_PLLCON1_PWRDOWN, 0),
262273
pll->reg_base + RK3036_PLLCON(1));
263-
rockchip_pll_wait_lock(pll);
274+
rockchip_rk3036_pll_wait_lock(pll);
264275

265276
return 0;
266277
}
@@ -589,19 +600,20 @@ static const struct clk_ops rockchip_rk3066_pll_clk_ops = {
589600
static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll)
590601
{
591602
u32 pllcon;
592-
int delay = 24000000;
593-
594-
/* poll check the lock status in rk3399 xPLLCON2 */
595-
while (delay > 0) {
596-
pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
597-
if (pllcon & RK3399_PLLCON2_LOCK_STATUS)
598-
return 0;
603+
int ret;
599604

600-
delay--;
601-
}
605+
/*
606+
* Lock time typical 250, max 500 input clock cycles @24MHz
607+
* So define a very safe maximum of 1000us, meaning 24000 cycles.
608+
*/
609+
ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2),
610+
pllcon,
611+
pllcon & RK3399_PLLCON2_LOCK_STATUS,
612+
0, 1000);
613+
if (ret)
614+
pr_err("%s: timeout waiting for pll to lock\n", __func__);
602615

603-
pr_err("%s: timeout waiting for pll to lock\n", __func__);
604-
return -ETIMEDOUT;
616+
return ret;
605617
}
606618

607619
static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll,

drivers/clk/rockchip/clk-rk3188.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -751,6 +751,7 @@ static const char *const rk3188_critical_clocks[] __initconst = {
751751
"pclk_peri",
752752
"hclk_cpubus",
753753
"hclk_vio_bus",
754+
"sclk_mac_lbtest",
754755
};
755756

756757
static struct rockchip_clk_provider *__init rk3188_common_clk_init(struct device_node *np)

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