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lumag
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phy: qualcomm: qmp-combo: add support for SAR2130P
Extend the USB+DP combo QMP PHY driver to support the SAR2130P platform. It mosly follows the SM8550 QMP PHY, but the QSERDES programming differs, most likely because of the parent clock rate differences. NOTE: The DP part wasn't yet tested, but it is not possible to support just the USB part of the PHY. DP part might require additional fixes later. Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Vinod Koul <[email protected]>
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‎drivers/phy/qualcomm/phy-qcom-qmp-combo.c

Lines changed: 100 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -400,6 +400,57 @@ static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
400400
QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
401401
};
402402

403+
static const struct qmp_phy_init_tbl sar2130p_usb3_serdes_tbl[] = {
404+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x55),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x0e),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x2e),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x82),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xd5),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xb7),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb7),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x55),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x0e),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x12),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x34),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x04),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xd5),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
440+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),
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QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14),
445+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
446+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20),
447+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x04),
448+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
449+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),
450+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),
451+
QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c),
452+
};
453+
403454
static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = {
404455
QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
405456
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
@@ -1730,6 +1781,51 @@ static const struct qmp_combo_offsets qmp_combo_offsets_v5 = {
17301781
.dp_dp_phy = 0x2200,
17311782
};
17321783

1784+
static const struct qmp_phy_cfg sar2130p_usb3dpphy_cfg = {
1785+
.offsets = &qmp_combo_offsets_v3,
1786+
1787+
.serdes_tbl = sar2130p_usb3_serdes_tbl,
1788+
.serdes_tbl_num = ARRAY_SIZE(sar2130p_usb3_serdes_tbl),
1789+
.tx_tbl = sm8550_usb3_tx_tbl,
1790+
.tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl),
1791+
.rx_tbl = sm8550_usb3_rx_tbl,
1792+
.rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl),
1793+
.pcs_tbl = sm8550_usb3_pcs_tbl,
1794+
.pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl),
1795+
.pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl,
1796+
.pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl),
1797+
1798+
.dp_serdes_tbl = qmp_v6_dp_serdes_tbl,
1799+
.dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
1800+
.dp_tx_tbl = qmp_v6_dp_tx_tbl,
1801+
.dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
1802+
1803+
.serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr,
1804+
.serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
1805+
.serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr,
1806+
.serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
1807+
.serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2,
1808+
.serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
1809+
.serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3,
1810+
.serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
1811+
1812+
.swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr,
1813+
.pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr,
1814+
.swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
1815+
.pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
1816+
1817+
.dp_aux_init = qmp_v4_dp_aux_init,
1818+
.configure_dp_tx = qmp_v4_configure_dp_tx,
1819+
.configure_dp_phy = qmp_v4_configure_dp_phy,
1820+
.calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
1821+
1822+
.regs = qmp_v6_usb3phy_regs_layout,
1823+
.reset_list = msm8996_usb3phy_reset_l,
1824+
.num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1825+
.vreg_list = qmp_phy_vreg_l,
1826+
.num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1827+
};
1828+
17331829
static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = {
17341830
.offsets = &qmp_combo_offsets_v3,
17351831

@@ -3767,6 +3863,10 @@ static int qmp_combo_probe(struct platform_device *pdev)
37673863
}
37683864

37693865
static const struct of_device_id qmp_combo_of_match_table[] = {
3866+
{
3867+
.compatible = "qcom,sar2130p-qmp-usb3-dp-phy",
3868+
.data = &sar2130p_usb3dpphy_cfg,
3869+
},
37703870
{
37713871
.compatible = "qcom,sc7180-qmp-usb3-dp-phy",
37723872
.data = &sc7180_usb3dpphy_cfg,

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