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Commit 552ae76

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Marc Zyngier
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arm64: Detect the ARMv8.4 TTL feature
In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL feature allows TLBs to be issued with a level allowing for quicker invalidation. Let's detect the feature for now. Further patches will implement its actual usage. Reviewed-by : Suzuki K Polose <[email protected]> Reviewed-by: Catalin Marinas <[email protected]> Signed-off-by: Marc Zyngier <[email protected]>
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arch/arm64/include/asm/cpucaps.h

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@@ -62,7 +62,8 @@
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#define ARM64_HAS_GENERIC_AUTH 52
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#define ARM64_HAS_32BIT_EL1 53
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#define ARM64_BTI 54
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#define ARM64_HAS_ARMv8_4_TTL 55
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#define ARM64_NCAPS 55
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#define ARM64_NCAPS 56
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#endif /* __ASM_CPUCAPS_H */

arch/arm64/include/asm/sysreg.h

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@@ -746,6 +746,7 @@
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/* id_aa64mmfr2 */
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#define ID_AA64MMFR2_E0PD_SHIFT 60
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#define ID_AA64MMFR2_TTL_SHIFT 48
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#define ID_AA64MMFR2_FWB_SHIFT 40
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#define ID_AA64MMFR2_AT_SHIFT 32
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#define ID_AA64MMFR2_LVA_SHIFT 16

arch/arm64/kernel/cpufeature.c

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@@ -323,6 +323,7 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr1[] = {
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static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = {
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_E0PD_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_TTL_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_FWB_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_VISIBLE, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_AT_SHIFT, 4, 0),
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ARM64_FTR_BITS(FTR_HIDDEN, FTR_STRICT, FTR_LOWER_SAFE, ID_AA64MMFR2_LVA_SHIFT, 4, 0),
@@ -1882,6 +1883,16 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
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.matches = has_cpuid_feature,
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.cpu_enable = cpu_has_fwb,
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},
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{
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.desc = "ARMv8.4 Translation Table Level",
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.type = ARM64_CPUCAP_SYSTEM_FEATURE,
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.capability = ARM64_HAS_ARMv8_4_TTL,
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.sys_reg = SYS_ID_AA64MMFR2_EL1,
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.sign = FTR_UNSIGNED,
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.field_pos = ID_AA64MMFR2_TTL_SHIFT,
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.min_field_value = 1,
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.matches = has_cpuid_feature,
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},
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#ifdef CONFIG_ARM64_HW_AFDBM
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{
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/*

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