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Zhao Qunqinbp3tk0v
Zhao Qunqin
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bp3tk0v
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EDAC: Add an EDAC driver for the Loongson memory controller
Add ECC support for Loongson SoC DDR controller. This driver reports single bit errors (CE) only. Only ACPI firmware is supported. [ bp: Document what last_ce_count is for. ] Signed-off-by: Zhao Qunqin <[email protected]> Signed-off-by: Borislav Petkov (AMD) <[email protected]> Reviewed-by: Huacai Chen <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Borislav Petkov (AMD) <[email protected]>
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‎MAINTAINERS

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@@ -13544,6 +13544,12 @@ S: Maintained
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F: Documentation/devicetree/bindings/thermal/loongson,ls2k-thermal.yaml
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F: drivers/thermal/loongson2_thermal.c
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LOONGSON EDAC DRIVER
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M: Zhao Qunqin <[email protected]>
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L: [email protected]
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S: Maintained
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F: drivers/edac/loongson_edac.c
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LSILOGIC MPT FUSION DRIVERS (FC/SAS/SPI)
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M: Sathya Prakash <[email protected]>
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M: Sreekanth Reddy <[email protected]>

‎arch/loongarch/Kconfig

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@@ -81,6 +81,7 @@ config LOONGARCH
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select BUILDTIME_TABLE_SORT
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select COMMON_CLK
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select CPU_PM
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select EDAC_SUPPORT
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select EFI
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select GENERIC_CLOCKEVENTS
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select GENERIC_CMOS_UPDATE

‎drivers/edac/Kconfig

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@@ -546,5 +546,13 @@ config EDAC_VERSAL
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Support injecting both correctable and uncorrectable errors
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for debugging purposes.
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config EDAC_LOONGSON
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tristate "Loongson Memory Controller"
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depends on LOONGARCH && ACPI
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help
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Support for error detection and correction on the Loongson
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family memory controller. This driver reports single bit
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errors (CE) only. Loongson-3A5000/3C5000/3D5000/3A6000/3C6000
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are compatible.
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endif # EDAC

‎drivers/edac/Makefile

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@@ -86,3 +86,4 @@ obj-$(CONFIG_EDAC_DMC520) += dmc520_edac.o
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obj-$(CONFIG_EDAC_NPCM) += npcm_edac.o
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obj-$(CONFIG_EDAC_ZYNQMP) += zynqmp_edac.o
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obj-$(CONFIG_EDAC_VERSAL) += versal_edac.o
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obj-$(CONFIG_EDAC_LOONGSON) += loongson_edac.o

‎drivers/edac/loongson_edac.c

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// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2024 Loongson Technology Corporation Limited.
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*/
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#include <linux/acpi.h>
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#include <linux/edac.h>
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#include <linux/init.h>
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#include <linux/io-64-nonatomic-lo-hi.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include "edac_module.h"
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#define ECC_CS_COUNT_REG 0x18
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struct loongson_edac_pvt {
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void __iomem *ecc_base;
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/*
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* The ECC register in this controller records the number of errors
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* encountered since reset and cannot be zeroed so in order to be able
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* to report the error count at each check, this records the previous
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* register state.
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*/
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int last_ce_count;
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};
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static int read_ecc(struct mem_ctl_info *mci)
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{
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struct loongson_edac_pvt *pvt = mci->pvt_info;
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u64 ecc;
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int cs;
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ecc = readq(pvt->ecc_base + ECC_CS_COUNT_REG);
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/* cs0 -- cs3 */
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cs = ecc & 0xff;
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cs += (ecc >> 8) & 0xff;
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cs += (ecc >> 16) & 0xff;
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cs += (ecc >> 24) & 0xff;
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return cs;
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}
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static void edac_check(struct mem_ctl_info *mci)
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{
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struct loongson_edac_pvt *pvt = mci->pvt_info;
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int new, add;
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new = read_ecc(mci);
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add = new - pvt->last_ce_count;
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pvt->last_ce_count = new;
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if (add <= 0)
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return;
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edac_mc_handle_error(HW_EVENT_ERR_CORRECTED, mci, add,
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0, 0, 0, 0, 0, -1, "error", "");
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}
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static void dimm_config_init(struct mem_ctl_info *mci)
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{
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struct dimm_info *dimm;
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u32 size, npages;
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/* size not used */
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size = -1;
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npages = MiB_TO_PAGES(size);
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dimm = edac_get_dimm(mci, 0, 0, 0);
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dimm->nr_pages = npages;
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snprintf(dimm->label, sizeof(dimm->label),
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"MC#%uChannel#%u_DIMM#%u", mci->mc_idx, 0, 0);
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dimm->grain = 8;
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}
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static void pvt_init(struct mem_ctl_info *mci, void __iomem *vbase)
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{
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struct loongson_edac_pvt *pvt = mci->pvt_info;
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pvt->ecc_base = vbase;
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pvt->last_ce_count = read_ecc(mci);
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}
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static int edac_probe(struct platform_device *pdev)
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{
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struct edac_mc_layer layers[2];
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struct mem_ctl_info *mci;
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void __iomem *vbase;
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int ret;
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vbase = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(vbase))
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return PTR_ERR(vbase);
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layers[0].type = EDAC_MC_LAYER_CHANNEL;
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layers[0].size = 1;
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layers[0].is_virt_csrow = false;
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layers[1].type = EDAC_MC_LAYER_SLOT;
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layers[1].size = 1;
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layers[1].is_virt_csrow = true;
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mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers,
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sizeof(struct loongson_edac_pvt));
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if (mci == NULL)
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return -ENOMEM;
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mci->mc_idx = edac_device_alloc_index();
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mci->mtype_cap = MEM_FLAG_RDDR4;
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mci->edac_ctl_cap = EDAC_FLAG_NONE;
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mci->edac_cap = EDAC_FLAG_NONE;
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mci->mod_name = "loongson_edac.c";
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mci->ctl_name = "loongson_edac_ctl";
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mci->dev_name = "loongson_edac_dev";
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mci->ctl_page_to_phys = NULL;
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mci->pdev = &pdev->dev;
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mci->error_desc.grain = 8;
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mci->edac_check = edac_check;
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pvt_init(mci, vbase);
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dimm_config_init(mci);
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ret = edac_mc_add_mc(mci);
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if (ret) {
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edac_dbg(0, "MC: failed edac_mc_add_mc()\n");
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edac_mc_free(mci);
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return ret;
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}
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edac_op_state = EDAC_OPSTATE_POLL;
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return 0;
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}
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static void edac_remove(struct platform_device *pdev)
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{
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struct mem_ctl_info *mci = edac_mc_del_mc(&pdev->dev);
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if (mci)
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edac_mc_free(mci);
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}
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static const struct acpi_device_id loongson_edac_acpi_match[] = {
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{"LOON0010", 0},
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{}
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};
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MODULE_DEVICE_TABLE(acpi, loongson_edac_acpi_match);
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static struct platform_driver loongson_edac_driver = {
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.probe = edac_probe,
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.remove = edac_remove,
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.driver = {
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.name = "loongson-mc-edac",
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.acpi_match_table = loongson_edac_acpi_match,
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},
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};
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module_platform_driver(loongson_edac_driver);
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MODULE_LICENSE("GPL");
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MODULE_AUTHOR("Zhao Qunqin <[email protected]>");
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MODULE_DESCRIPTION("EDAC driver for loongson memory controller");

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