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126 | 126 | interrupt-controller;
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127 | 127 | #interrupt-cells = <3>;
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128 | 128 |
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| 129 | + rgmii0_pins: rgmii0-pins { |
| 130 | + pins = "PH0", "PH1", "PH2", "PH3", "PH4", |
| 131 | + "PH5", "PH6", "PH7", "PH9", "PH10", |
| 132 | + "PH14", "PH15", "PH16", "PH17", "PH18"; |
| 133 | + allwinner,pinmux = <5>; |
| 134 | + function = "emac0"; |
| 135 | + drive-strength = <40>; |
| 136 | + bias-disable; |
| 137 | + }; |
| 138 | + |
129 | 139 | mmc0_pins: mmc0-pins {
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130 | 140 | pins = "PF0" ,"PF1", "PF2", "PF3", "PF4", "PF5";
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131 | 141 | allwinner,pinmux = <2>;
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409 | 419 | #size-cells = <0>;
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410 | 420 | };
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411 | 421 |
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| 422 | + syscon: syscon@3000000 { |
| 423 | + compatible = "allwinner,sun55i-a523-system-control", |
| 424 | + "allwinner,sun50i-a64-system-control"; |
| 425 | + reg = <0x03000000 0x1000>; |
| 426 | + #address-cells = <1>; |
| 427 | + #size-cells = <1>; |
| 428 | + ranges; |
| 429 | + }; |
| 430 | + |
412 | 431 | gic: interrupt-controller@3400000 {
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413 | 432 | compatible = "arm,gic-v3";
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414 | 433 | #address-cells = <1>;
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521 | 540 | status = "disabled";
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522 | 541 | };
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523 | 542 |
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| 543 | + emac0: ethernet@4500000 { |
| 544 | + compatible = "allwinner,sun55i-a523-emac0", |
| 545 | + "allwinner,sun50i-a64-emac"; |
| 546 | + reg = <0x04500000 0x10000>; |
| 547 | + clocks = <&ccu CLK_BUS_EMAC0>; |
| 548 | + clock-names = "stmmaceth"; |
| 549 | + resets = <&ccu RST_BUS_EMAC0>; |
| 550 | + reset-names = "stmmaceth"; |
| 551 | + interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; |
| 552 | + interrupt-names = "macirq"; |
| 553 | + pinctrl-names = "default"; |
| 554 | + pinctrl-0 = <&rgmii0_pins>; |
| 555 | + syscon = <&syscon>; |
| 556 | + status = "disabled"; |
| 557 | + |
| 558 | + mdio0: mdio { |
| 559 | + compatible = "snps,dwmac-mdio"; |
| 560 | + #address-cells = <1>; |
| 561 | + #size-cells = <0>; |
| 562 | + }; |
| 563 | + }; |
| 564 | + |
524 | 565 | r_ccu: clock-controller@7010000 {
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525 | 566 | compatible = "allwinner,sun55i-a523-r-ccu";
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526 | 567 | reg = <0x7010000 0x250>;
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