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Merge branch 'pci/ctrl/xilinx-cpm'
- Add DT binding and driver support for Versal CPM5 Gen5 Root Port (Bharat Kumar Gogada) * pci/ctrl/xilinx-cpm: MAINTAINERS: Add Xilinx Versal CPM Root Port maintainers PCI: xilinx-cpm: Add support for Versal CPM5 Root Port dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
2 parents a91c6db + 4e6217e commit 56ebef0

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Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml

Lines changed: 37 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,17 +14,23 @@ allOf:
1414

1515
properties:
1616
compatible:
17-
const: xlnx,versal-cpm-host-1.00
17+
enum:
18+
- xlnx,versal-cpm-host-1.00
19+
- xlnx,versal-cpm5-host
1820

1921
reg:
2022
items:
2123
- description: CPM system level control and status registers.
2224
- description: Configuration space region and bridge registers.
25+
- description: CPM5 control and status registers.
26+
minItems: 2
2327

2428
reg-names:
2529
items:
2630
- const: cpm_slcr
2731
- const: cfg
32+
- const: cpm_csr
33+
minItems: 2
2834

2935
interrupts:
3036
maxItems: 1
@@ -95,4 +101,34 @@ examples:
95101
interrupt-controller;
96102
};
97103
};
104+
105+
cpm5_pcie: pcie@fcdd0000 {
106+
compatible = "xlnx,versal-cpm5-host";
107+
device_type = "pci";
108+
#address-cells = <3>;
109+
#interrupt-cells = <1>;
110+
#size-cells = <2>;
111+
interrupts = <0 72 4>;
112+
interrupt-parent = <&gic>;
113+
interrupt-map-mask = <0 0 0 7>;
114+
interrupt-map = <0 0 0 1 &pcie_intc_1 0>,
115+
<0 0 0 2 &pcie_intc_1 1>,
116+
<0 0 0 3 &pcie_intc_1 2>,
117+
<0 0 0 4 &pcie_intc_1 3>;
118+
bus-range = <0x00 0xff>;
119+
ranges = <0x02000000 0x0 0xe0000000 0x0 0xe0000000 0x0 0x10000000>,
120+
<0x43000000 0x80 0x00000000 0x80 0x00000000 0x0 0x80000000>;
121+
msi-map = <0x0 &its_gic 0x0 0x10000>;
122+
reg = <0x00 0xfcdd0000 0x00 0x1000>,
123+
<0x06 0x00000000 0x00 0x1000000>,
124+
<0x00 0xfce20000 0x00 0x1000000>;
125+
reg-names = "cpm_slcr", "cfg", "cpm_csr";
126+
127+
pcie_intc_1: interrupt-controller {
128+
#address-cells = <0>;
129+
#interrupt-cells = <1>;
130+
interrupt-controller;
131+
};
132+
};
133+
98134
};

MAINTAINERS

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15540,6 +15540,14 @@ L: [email protected]
1554015540
S: Maintained
1554115541
F: drivers/pci/controller/dwc/*spear*
1554215542

15543+
PCI DRIVER FOR XILINX VERSAL CPM
15544+
M: Bharat Kumar Gogada <[email protected]>
15545+
M: Michal Simek <[email protected]>
15546+
15547+
S: Maintained
15548+
F: Documentation/devicetree/bindings/pci/xilinx-versal-cpm.yaml
15549+
F: drivers/pci/controller/pcie-xilinx-cpm.c
15550+
1554315551
PCMCIA SUBSYSTEM
1554415552
M: Dominik Brodowski <[email protected]>
1554515553
S: Odd Fixes

drivers/pci/controller/pcie-xilinx-cpm.c

Lines changed: 58 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -35,6 +35,10 @@
3535
#define XILINX_CPM_PCIE_MISC_IR_ENABLE 0x00000348
3636
#define XILINX_CPM_PCIE_MISC_IR_LOCAL BIT(1)
3737

38+
#define XILINX_CPM_PCIE_IR_STATUS 0x000002A0
39+
#define XILINX_CPM_PCIE_IR_ENABLE 0x000002A8
40+
#define XILINX_CPM_PCIE_IR_LOCAL BIT(0)
41+
3842
/* Interrupt registers definitions */
3943
#define XILINX_CPM_PCIE_INTR_LINK_DOWN 0
4044
#define XILINX_CPM_PCIE_INTR_HOT_RESET 3
@@ -98,6 +102,19 @@
98102
/* Phy Status/Control Register definitions */
99103
#define XILINX_CPM_PCIE_REG_PSCR_LNKUP BIT(11)
100104

105+
enum xilinx_cpm_version {
106+
CPM,
107+
CPM5,
108+
};
109+
110+
/**
111+
* struct xilinx_cpm_variant - CPM variant information
112+
* @version: CPM version
113+
*/
114+
struct xilinx_cpm_variant {
115+
enum xilinx_cpm_version version;
116+
};
117+
101118
/**
102119
* struct xilinx_cpm_pcie - PCIe port information
103120
* @dev: Device pointer
@@ -109,6 +126,7 @@
109126
* @intx_irq: legacy interrupt number
110127
* @irq: Error interrupt number
111128
* @lock: lock protecting shared register access
129+
* @variant: CPM version check pointer
112130
*/
113131
struct xilinx_cpm_pcie {
114132
struct device *dev;
@@ -120,6 +138,7 @@ struct xilinx_cpm_pcie {
120138
int intx_irq;
121139
int irq;
122140
raw_spinlock_t lock;
141+
const struct xilinx_cpm_variant *variant;
123142
};
124143

125144
static u32 pcie_read(struct xilinx_cpm_pcie *port, u32 reg)
@@ -285,6 +304,13 @@ static void xilinx_cpm_pcie_event_flow(struct irq_desc *desc)
285304
generic_handle_domain_irq(port->cpm_domain, i);
286305
pcie_write(port, val, XILINX_CPM_PCIE_REG_IDR);
287306

307+
if (port->variant->version == CPM5) {
308+
val = readl_relaxed(port->cpm_base + XILINX_CPM_PCIE_IR_STATUS);
309+
if (val)
310+
writel_relaxed(val, port->cpm_base +
311+
XILINX_CPM_PCIE_IR_STATUS);
312+
}
313+
288314
/*
289315
* XILINX_CPM_PCIE_MISC_IR_STATUS register is mapped to
290316
* CPM SLCR block.
@@ -484,6 +510,12 @@ static void xilinx_cpm_pcie_init_port(struct xilinx_cpm_pcie *port)
484510
*/
485511
writel(XILINX_CPM_PCIE_MISC_IR_LOCAL,
486512
port->cpm_base + XILINX_CPM_PCIE_MISC_IR_ENABLE);
513+
514+
if (port->variant->version == CPM5) {
515+
writel(XILINX_CPM_PCIE_IR_LOCAL,
516+
port->cpm_base + XILINX_CPM_PCIE_IR_ENABLE);
517+
}
518+
487519
/* Enable the Bridge enable bit */
488520
pcie_write(port, pcie_read(port, XILINX_CPM_PCIE_REG_RPSC) |
489521
XILINX_CPM_PCIE_REG_RPSC_BEN,
@@ -518,7 +550,14 @@ static int xilinx_cpm_pcie_parse_dt(struct xilinx_cpm_pcie *port,
518550
if (IS_ERR(port->cfg))
519551
return PTR_ERR(port->cfg);
520552

521-
port->reg_base = port->cfg->win;
553+
if (port->variant->version == CPM5) {
554+
port->reg_base = devm_platform_ioremap_resource_byname(pdev,
555+
"cpm_csr");
556+
if (IS_ERR(port->reg_base))
557+
return PTR_ERR(port->reg_base);
558+
} else {
559+
port->reg_base = port->cfg->win;
560+
}
522561

523562
return 0;
524563
}
@@ -559,6 +598,8 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
559598
if (!bus)
560599
return -ENODEV;
561600

601+
port->variant = of_device_get_match_data(dev);
602+
562603
err = xilinx_cpm_pcie_parse_dt(port, bus->res);
563604
if (err) {
564605
dev_err(dev, "Parsing DT failed\n");
@@ -591,8 +632,23 @@ static int xilinx_cpm_pcie_probe(struct platform_device *pdev)
591632
return err;
592633
}
593634

635+
static const struct xilinx_cpm_variant cpm_host = {
636+
.version = CPM,
637+
};
638+
639+
static const struct xilinx_cpm_variant cpm5_host = {
640+
.version = CPM5,
641+
};
642+
594643
static const struct of_device_id xilinx_cpm_pcie_of_match[] = {
595-
{ .compatible = "xlnx,versal-cpm-host-1.00", },
644+
{
645+
.compatible = "xlnx,versal-cpm-host-1.00",
646+
.data = &cpm_host,
647+
},
648+
{
649+
.compatible = "xlnx,versal-cpm5-host",
650+
.data = &cpm5_host,
651+
},
596652
{}
597653
};
598654

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