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drm/i915: Store CS timestamp frequency in Hz
kHz isn't accurate enough for storing the CS timestamp frequency on some of the platforms. Store the value in Hz instead. Cc: Lionel Landwerlin <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Chris Wilson <[email protected]> Reviewed-by: Lionel Landwerlin <[email protected]>
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+30
-30
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6 files changed

+30
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‎drivers/gpu/drm/i915/i915_debugfs.c

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1304,8 +1304,8 @@ static int i915_engine_info(struct seq_file *m, void *unused)
13041304
seq_printf(m, "GT awake? %s [%d]\n",
13051305
yesno(dev_priv->gt.awake),
13061306
atomic_read(&dev_priv->gt.wakeref.count));
1307-
seq_printf(m, "CS timestamp frequency: %u kHz\n",
1308-
RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_khz);
1307+
seq_printf(m, "CS timestamp frequency: %u Hz\n",
1308+
RUNTIME_INFO(dev_priv)->cs_timestamp_frequency_hz);
13091309

13101310
p = drm_seq_file_printer(m);
13111311
for_each_uabi_engine(engine, dev_priv)
@@ -1404,7 +1404,7 @@ static int
14041404
i915_perf_noa_delay_set(void *data, u64 val)
14051405
{
14061406
struct drm_i915_private *i915 = data;
1407-
const u32 clk = RUNTIME_INFO(i915)->cs_timestamp_frequency_khz;
1407+
const u32 clk = RUNTIME_INFO(i915)->cs_timestamp_frequency_hz / 1000;
14081408

14091409
/*
14101410
* This would lead to infinite waits as we're doing timestamp

‎drivers/gpu/drm/i915/i915_getparam.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -153,7 +153,7 @@ int i915_getparam_ioctl(struct drm_device *dev, void *data,
153153
return -ENODEV;
154154
break;
155155
case I915_PARAM_CS_TIMESTAMP_FREQUENCY:
156-
value = 1000 * RUNTIME_INFO(i915)->cs_timestamp_frequency_khz;
156+
value = RUNTIME_INFO(i915)->cs_timestamp_frequency_hz;
157157
break;
158158
case I915_PARAM_MMAP_GTT_COHERENT:
159159
value = INTEL_INFO(i915)->has_coherent_ggtt;

‎drivers/gpu/drm/i915/i915_perf.c

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1613,8 +1613,8 @@ static int alloc_noa_wait(struct i915_perf_stream *stream)
16131613
struct i915_vma *vma;
16141614
const u64 delay_ticks = 0xffffffffffffffff -
16151615
DIV_ROUND_UP_ULL(atomic64_read(&stream->perf->noa_programming_delay) *
1616-
RUNTIME_INFO(i915)->cs_timestamp_frequency_khz,
1617-
1000000);
1616+
RUNTIME_INFO(i915)->cs_timestamp_frequency_hz,
1617+
1000000000);
16181618
const u32 base = stream->engine->mmio_base;
16191619
#define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
16201620
u32 *batch, *ts0, *cs, *jump;
@@ -3484,8 +3484,8 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
34843484

34853485
static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
34863486
{
3487-
return div_u64(1000000 * (2ULL << exponent),
3488-
RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_khz);
3487+
return div_u64(1000000000 * (2ULL << exponent),
3488+
RUNTIME_INFO(perf->i915)->cs_timestamp_frequency_hz);
34893489
}
34903490

34913491
/**
@@ -4343,8 +4343,8 @@ void i915_perf_init(struct drm_i915_private *i915)
43434343
if (perf->ops.enable_metric_set) {
43444344
mutex_init(&perf->lock);
43454345

4346-
oa_sample_rate_hard_limit = 1000 *
4347-
(RUNTIME_INFO(i915)->cs_timestamp_frequency_khz / 2);
4346+
oa_sample_rate_hard_limit =
4347+
RUNTIME_INFO(i915)->cs_timestamp_frequency_hz / 2;
43484348

43494349
mutex_init(&perf->metrics_lock);
43504350
idr_init(&perf->metrics_idr);

‎drivers/gpu/drm/i915/intel_device_info.c

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -136,8 +136,8 @@ void intel_device_info_print_runtime(const struct intel_runtime_info *info,
136136
sseu_dump(&info->sseu, p);
137137

138138
drm_printf(p, "rawclk rate: %u kHz\n", info->rawclk_freq);
139-
drm_printf(p, "CS timestamp frequency: %u kHz\n",
140-
info->cs_timestamp_frequency_khz);
139+
drm_printf(p, "CS timestamp frequency: %u Hz\n",
140+
info->cs_timestamp_frequency_hz);
141141
}
142142

143143
static int sseu_eu_idx(const struct sseu_dev_info *sseu, int slice,
@@ -678,21 +678,21 @@ static u32 read_reference_ts_freq(struct drm_i915_private *dev_priv)
678678

679679
base_freq = ((ts_override & GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK) >>
680680
GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_SHIFT) + 1;
681-
base_freq *= 1000;
681+
base_freq *= 1000000;
682682

683683
frac_freq = ((ts_override &
684684
GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK) >>
685685
GEN9_TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_SHIFT);
686-
frac_freq = 1000 / (frac_freq + 1);
686+
frac_freq = 1000000 / (frac_freq + 1);
687687

688688
return base_freq + frac_freq;
689689
}
690690

691691
static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
692692
u32 rpm_config_reg)
693693
{
694-
u32 f19_2_mhz = 19200;
695-
u32 f24_mhz = 24000;
694+
u32 f19_2_mhz = 19200000;
695+
u32 f24_mhz = 24000000;
696696
u32 crystal_clock = (rpm_config_reg &
697697
GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
698698
GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
@@ -711,10 +711,10 @@ static u32 gen10_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
711711
static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
712712
u32 rpm_config_reg)
713713
{
714-
u32 f19_2_mhz = 19200;
715-
u32 f24_mhz = 24000;
716-
u32 f25_mhz = 25000;
717-
u32 f38_4_mhz = 38400;
714+
u32 f19_2_mhz = 19200000;
715+
u32 f24_mhz = 24000000;
716+
u32 f25_mhz = 25000000;
717+
u32 f38_4_mhz = 38400000;
718718
u32 crystal_clock = (rpm_config_reg &
719719
GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
720720
GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
@@ -736,9 +736,9 @@ static u32 gen11_get_crystal_clock_freq(struct drm_i915_private *dev_priv,
736736

737737
static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
738738
{
739-
u32 f12_5_mhz = 12500;
740-
u32 f19_2_mhz = 19200;
741-
u32 f24_mhz = 24000;
739+
u32 f12_5_mhz = 12500000;
740+
u32 f19_2_mhz = 19200000;
741+
u32 f24_mhz = 24000000;
742742

743743
if (INTEL_GEN(dev_priv) <= 4) {
744744
/* PRMs say:
@@ -747,7 +747,7 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
747747
* hclks." (through the “Clocking Configuration”
748748
* (“CLKCFG”) MCHBAR register)
749749
*/
750-
return RUNTIME_INFO(dev_priv)->rawclk_freq / 16;
750+
return RUNTIME_INFO(dev_priv)->rawclk_freq * 1000 / 16;
751751
} else if (INTEL_GEN(dev_priv) <= 8) {
752752
/* PRMs say:
753753
*
@@ -1048,11 +1048,11 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
10481048
drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
10491049

10501050
/* Initialize command stream timestamp frequency */
1051-
runtime->cs_timestamp_frequency_khz =
1051+
runtime->cs_timestamp_frequency_hz =
10521052
read_timestamp_frequency(dev_priv);
1053-
if (runtime->cs_timestamp_frequency_khz) {
1053+
if (runtime->cs_timestamp_frequency_hz) {
10541054
runtime->cs_timestamp_period_ns =
1055-
div_u64(1e6, runtime->cs_timestamp_frequency_khz);
1055+
div_u64(1e9, runtime->cs_timestamp_frequency_hz);
10561056
drm_dbg(&dev_priv->drm,
10571057
"CS timestamp wraparound in %lldms\n",
10581058
div_u64(mul_u32_u32(runtime->cs_timestamp_period_ns,

‎drivers/gpu/drm/i915/intel_device_info.h

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -221,7 +221,7 @@ struct intel_runtime_info {
221221

222222
u32 rawclk_freq;
223223

224-
u32 cs_timestamp_frequency_khz;
224+
u32 cs_timestamp_frequency_hz;
225225
u32 cs_timestamp_period_ns;
226226

227227
/* Media engine access to SFC per instance */

‎drivers/gpu/drm/i915/selftests/i915_perf.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -262,8 +262,8 @@ static int live_noa_delay(void *arg)
262262

263263
delay = intel_read_status_page(stream->engine, 0x102);
264264
delay -= intel_read_status_page(stream->engine, 0x100);
265-
delay = div_u64(mul_u32_u32(delay, 1000 * 1000),
266-
RUNTIME_INFO(i915)->cs_timestamp_frequency_khz);
265+
delay = div_u64(mul_u32_u32(delay, 1000000000),
266+
RUNTIME_INFO(i915)->cs_timestamp_frequency_hz);
267267
pr_info("GPU delay: %uns, expected %lluns\n",
268268
delay, expected);
269269

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