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Anshuman Khandualctmarinas
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arm64/mm: Stop using ESR_ELx_FSC_TYPE during fault
Fault status codes at page table level 0, 1, 2 and 3 for access, permission and translation faults are architecturally organized in a way, that masking out ESR_ELx_FSC_TYPE, fetches Level 0 status code for the respective fault. Helpers like esr_fsc_is_[translation|permission|access_flag]_fault() mask out ESR_ELx_FSC_TYPE before comparing against corresponding Level 0 status code as the kernel does not yet care about the page table level, where in the fault really occurred previously. This scheme is starting to crumble after FEAT_LPA2 when level -1 got added. Fault status code for translation fault at level -1 is 0x2B which does not follow ESR_ELx_FSC_TYPE, requiring esr_fsc_is_translation_fault() changes. This changes above helpers to compare against individual fault status code values for each page table level and stop using ESR_ELx_FSC_TYPE, which is losing its value as a common mask. Cc: Will Deacon <[email protected]> Cc: Marc Zyngier <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Anshuman Khandual <[email protected]> Reviewed-by: Marc Zyngier <[email protected]> Reviewed-by: Ryan Roberts <[email protected]> Acked-by: Mark Rutland <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Catalin Marinas <[email protected]>
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  • arch/arm64/include/asm

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arch/arm64/include/asm/esr.h

Lines changed: 27 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -121,6 +121,14 @@
121121
#define ESR_ELx_FSC_SECC (0x18)
122122
#define ESR_ELx_FSC_SECC_TTW(n) (0x1c + (n))
123123

124+
/* Status codes for individual page table levels */
125+
#define ESR_ELx_FSC_ACCESS_L(n) (ESR_ELx_FSC_ACCESS + n)
126+
#define ESR_ELx_FSC_PERM_L(n) (ESR_ELx_FSC_PERM + n)
127+
128+
#define ESR_ELx_FSC_FAULT_nL (0x2C)
129+
#define ESR_ELx_FSC_FAULT_L(n) (((n) < 0 ? ESR_ELx_FSC_FAULT_nL : \
130+
ESR_ELx_FSC_FAULT) + (n))
131+
124132
/* ISS field definitions for Data Aborts */
125133
#define ESR_ELx_ISV_SHIFT (24)
126134
#define ESR_ELx_ISV (UL(1) << ESR_ELx_ISV_SHIFT)
@@ -388,20 +396,33 @@ static inline bool esr_is_data_abort(unsigned long esr)
388396

389397
static inline bool esr_fsc_is_translation_fault(unsigned long esr)
390398
{
391-
/* Translation fault, level -1 */
392-
if ((esr & ESR_ELx_FSC) == 0b101011)
393-
return true;
394-
return (esr & ESR_ELx_FSC_TYPE) == ESR_ELx_FSC_FAULT;
399+
esr = esr & ESR_ELx_FSC;
400+
401+
return (esr == ESR_ELx_FSC_FAULT_L(3)) ||
402+
(esr == ESR_ELx_FSC_FAULT_L(2)) ||
403+
(esr == ESR_ELx_FSC_FAULT_L(1)) ||
404+
(esr == ESR_ELx_FSC_FAULT_L(0)) ||
405+
(esr == ESR_ELx_FSC_FAULT_L(-1));
395406
}
396407

397408
static inline bool esr_fsc_is_permission_fault(unsigned long esr)
398409
{
399-
return (esr & ESR_ELx_FSC_TYPE) == ESR_ELx_FSC_PERM;
410+
esr = esr & ESR_ELx_FSC;
411+
412+
return (esr == ESR_ELx_FSC_PERM_L(3)) ||
413+
(esr == ESR_ELx_FSC_PERM_L(2)) ||
414+
(esr == ESR_ELx_FSC_PERM_L(1)) ||
415+
(esr == ESR_ELx_FSC_PERM_L(0));
400416
}
401417

402418
static inline bool esr_fsc_is_access_flag_fault(unsigned long esr)
403419
{
404-
return (esr & ESR_ELx_FSC_TYPE) == ESR_ELx_FSC_ACCESS;
420+
esr = esr & ESR_ELx_FSC;
421+
422+
return (esr == ESR_ELx_FSC_ACCESS_L(3)) ||
423+
(esr == ESR_ELx_FSC_ACCESS_L(2)) ||
424+
(esr == ESR_ELx_FSC_ACCESS_L(1)) ||
425+
(esr == ESR_ELx_FSC_ACCESS_L(0));
405426
}
406427

407428
/* Indicate whether ESR.EC==0x1A is for an ERETAx instruction */

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