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Heiko Stuebnermmind
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drm/rockchip: vop2: fix rk3588 dp+dsi maxclk verification
The clock is in Hz while the value checked against is in kHz, so actual frequencies will never be able to be below to max value. Fix this by specifying the max-value in Hz too. Fixes: 5a028e8 ("drm/rockchip: vop2: Add support for rk3588") Signed-off-by: Heiko Stuebner <[email protected]> Reviewed-by: Quentin Schulz <[email protected]> Acked-by: Andy Yan <[email protected]> Reviewed-by: Sebastian Reichel <[email protected]> Tested-by: Sebastian Reichel <[email protected]> Signed-off-by: Heiko Stuebner <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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drivers/gpu/drm/rockchip/rockchip_drm_vop2.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1864,9 +1864,9 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id,
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else
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dclk_out_rate = v_pixclk >> 2;
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1867-
dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000);
1867+
dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000000);
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if (!dclk_rate) {
1869-
drm_err(vop2->drm, "DP dclk_out_rate out of range, dclk_out_rate: %ld KHZ\n",
1869+
drm_err(vop2->drm, "DP dclk_out_rate out of range, dclk_out_rate: %ld Hz\n",
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dclk_out_rate);
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return 0;
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}
@@ -1881,9 +1881,9 @@ static unsigned long rk3588_calc_cru_cfg(struct vop2_video_port *vp, int id,
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* dclk_rate = N * dclk_core_rate N = (1,2,4 ),
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* we get a little factor here
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*/
1884-
dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000);
1884+
dclk_rate = rk3588_calc_dclk(dclk_out_rate, 600000000);
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if (!dclk_rate) {
1886-
drm_err(vop2->drm, "MIPI dclk out of range, dclk_out_rate: %ld KHZ\n",
1886+
drm_err(vop2->drm, "MIPI dclk out of range, dclk_out_rate: %ld Hz\n",
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dclk_out_rate);
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return 0;
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}

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