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Merge tag 'iommu-updates-v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu
Pull iommu updates from Joerg Roedel: - Convert to platform remove callback returning void - Extend changing default domain to normal group - Intel VT-d updates: - Remove VT-d virtual command interface and IOASID - Allow the VT-d driver to support non-PRI IOPF - Remove PASID supervisor request support - Various small and misc cleanups - ARM SMMU updates: - Device-tree binding updates: * Allow Qualcomm GPU SMMUs to accept relevant clock properties * Document Qualcomm 8550 SoC as implementing an MMU-500 * Favour new "qcom,smmu-500" binding for Adreno SMMUs - Fix S2CR quirk detection on non-architectural Qualcomm SMMU implementations - Acknowledge SMMUv3 PRI queue overflow when consuming events - Document (in a comment) why ATS is disabled for bypass streams - AMD IOMMU updates: - 5-level page-table support - NUMA awareness for memory allocations - Unisoc driver: Support for reattaching an existing domain - Rockchip driver: Add missing set_platform_dma_ops callback - Mediatek driver: Adjust the dma-ranges - Various other small fixes and cleanups * tag 'iommu-updates-v6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (82 commits) iommu: Remove iommu_group_get_by_id() iommu: Make iommu_release_device() static iommu/vt-d: Remove BUG_ON in dmar_insert_dev_scope() iommu/vt-d: Remove a useless BUG_ON(dev->is_virtfn) iommu/vt-d: Remove BUG_ON in map/unmap() iommu/vt-d: Remove BUG_ON when domain->pgd is NULL iommu/vt-d: Remove BUG_ON in handling iotlb cache invalidation iommu/vt-d: Remove BUG_ON on checking valid pfn range iommu/vt-d: Make size of operands same in bitwise operations iommu/vt-d: Remove PASID supervisor request support iommu/vt-d: Use non-privileged mode for all PASIDs iommu/vt-d: Remove extern from function prototypes iommu/vt-d: Do not use GFP_ATOMIC when not needed iommu/vt-d: Remove unnecessary checks in iopf disabling path iommu/vt-d: Move PRI handling to IOPF feature path iommu/vt-d: Move pfsid and ats_qdep calculation to device probe path iommu/vt-d: Move iopf code from SVA to IOPF enabling path iommu/vt-d: Allow SVA with device-specific IOPF dmaengine: idxd: Add enable/disable device IOPF feature arm64: dts: mt8186: Add dma-ranges for the parent "soc" node ...
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Documentation/ABI/testing/sysfs-kernel-iommu_groups

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@@ -53,7 +53,6 @@ Description: /sys/kernel/iommu_groups/<grp_id>/type shows the type of default
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The default domain type of a group may be modified only when
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- The group has only one device.
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- The device in the group is not bound to any device driver.
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So, the users must unbind the appropriate driver before
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changing the default domain type.

Documentation/arch/x86/sva.rst

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@@ -107,7 +107,7 @@ process share the same page tables, thus the same MSR value.
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PASID Life Cycle Management
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===========================
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PASID is initialized as INVALID_IOASID (-1) when a process is created.
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PASID is initialized as IOMMU_PASID_INVALID (-1) when a process is created.
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Only processes that access SVA-capable devices need to have a PASID
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allocated. This allocation happens when a process opens/binds an SVA-capable

Documentation/devicetree/bindings/iommu/arm,smmu.yaml

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@@ -53,6 +53,7 @@ properties:
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- qcom,sm8250-smmu-500
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- qcom,sm8350-smmu-500
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- qcom,sm8450-smmu-500
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- qcom,sm8550-smmu-500
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- const: qcom,smmu-500
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- const: arm,mmu-500
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- qcom,sm8350-smmu-500
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- qcom,sm8450-smmu-500
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- const: arm,mmu-500
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- description: Qcom Adreno GPUs implementing "arm,smmu-500"
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- description: Qcom Adreno GPUs implementing "qcom,smmu-500" and "arm,mmu-500"
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items:
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- enum:
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- qcom,sc7280-smmu-500
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- qcom,sm6115-smmu-500
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- qcom,sm6125-smmu-500
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- qcom,sm8150-smmu-500
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- qcom,sm8250-smmu-500
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- qcom,sm8350-smmu-500
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- const: qcom,adreno-smmu
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- const: qcom,smmu-500
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- const: arm,mmu-500
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- description: Qcom Adreno GPUs implementing "arm,mmu-500" (legacy binding)
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deprecated: true
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items:
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# Do not add additional SoC to this list. Instead use previous list.
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- enum:
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- qcom,sc7280-smmu-500
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- qcom,sm8150-smmu-500
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- description: interface clock required to access smmu's registers
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through the TCU's programming interface.
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- if:
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properties:
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compatible:
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items:
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- enum:
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- qcom,sm6115-smmu-500
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- qcom,sm6125-smmu-500
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- const: qcom,adreno-smmu
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- const: qcom,smmu-500
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- const: arm,mmu-500
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then:
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properties:
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clock-names:
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items:
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- const: mem
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- const: hlos
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- const: iface
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clocks:
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items:
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- description: GPU memory bus clock
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- description: Voter clock required for HLOS SMMU access
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- description: Interface clock required for register access
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# Disallow clocks for all other platforms with specific compatibles
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- if:
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properties:
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- qcom,sdm845-smmu-500
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- qcom,sdx55-smmu-500
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- qcom,sdx65-smmu-500
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- qcom,sm6115-smmu-500
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- qcom,sm6125-smmu-500
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- qcom,sm6350-smmu-500
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- qcom,sm6375-smmu-500
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- qcom,sm8350-smmu-500
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- qcom,sm8450-smmu-500
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- qcom,sm8550-smmu-500
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then:
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properties:
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clock-names: false

Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml

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renesas,ipmmu-main:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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items:
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- items:
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- minItems: 1
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items:
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- description: phandle to main IPMMU
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- description: the interrupt bit number associated with the particular
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cache IPMMU device. The interrupt bit number needs to match the main
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IPMMU IMSSTR register. Only used by cache IPMMU instances.
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- description:
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The interrupt bit number associated with the particular cache
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IPMMU device. If present, the interrupt bit number needs to match
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the main IPMMU IMSSTR register. Only used by cache IPMMU
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instances.
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description:
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Reference to the main IPMMU phandle plus 1 cell. The cell is
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the interrupt bit number associated with the particular cache IPMMU
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device. The interrupt bit number needs to match the main IPMMU IMSSTR
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register. Only used by cache IPMMU instances.
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Reference to the main IPMMU.
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required:
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- compatible
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required:
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- power-domains
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- if:
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properties:
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compatible:
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contains:
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const: renesas,rcar-gen4-ipmmu-vmsa
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then:
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properties:
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renesas,ipmmu-main:
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items:
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- maxItems: 1
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else:
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properties:
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renesas,ipmmu-main:
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items:
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- minItems: 2
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examples:
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- |
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#include <dt-bindings/clock/r8a7791-cpg-mssr.h>

Documentation/devicetree/bindings/media/mediatek,mt8195-jpegdec.yaml

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Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
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Ports are according to the HW.
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dma-ranges:
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maxItems: 1
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description: |
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Describes the physical address space of IOMMU maps to memory.
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"#address-cells":
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const: 2
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- compatible
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- power-domains
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- iommus
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- dma-ranges
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- ranges
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additionalProperties: false
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<&iommu_vpp M4U_PORT_L19_JPGDEC_BSDMA1>,
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<&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
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<&iommu_vpp M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
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dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;

Documentation/devicetree/bindings/media/mediatek,mt8195-jpegenc.yaml

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Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
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Ports are according to the HW.
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dma-ranges:
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maxItems: 1
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description: |
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Describes the physical address space of IOMMU maps to memory.
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"#address-cells":
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const: 2
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- compatible
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- power-domains
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- iommus
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- dma-ranges
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- ranges
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additionalProperties: false
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<&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
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<&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
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<&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
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dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;

Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml

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List of the hardware port in respective IOMMU block for current Socs.
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Refer to bindings/iommu/mediatek,iommu.yaml.
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dma-ranges:
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maxItems: 1
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description: |
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Describes the physical address space of IOMMU maps to memory.
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mediatek,vpu:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:

Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml

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List of the hardware port in respective IOMMU block for current Socs.
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Refer to bindings/iommu/mediatek,iommu.yaml.
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dma-ranges:
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maxItems: 1
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description: |
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Describes the physical address space of IOMMU maps to memory.
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mediatek,vpu:
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$ref: /schemas/types.yaml#/definitions/phandle
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Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml

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Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details.
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Ports are according to the HW.
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dma-ranges:
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maxItems: 1
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description: |
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Describes the physical address space of IOMMU maps to memory.
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required:
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- compatible
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- reg

arch/arm64/boot/dts/mediatek/mt8186.dtsi

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#address-cells = <2>;
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#size-cells = <2>;
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compatible = "simple-bus";
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dma-ranges = <0x0 0x0 0x0 0x0 0x4 0x0>;
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ranges;
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gic: interrupt-controller@c000000 {

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