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airliedairlied
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Merge tag 'amd-drm-fixes-6.1-2022-11-16' of https://gitlab.freedesktop.org/agd5f/linux into drm-fixes
amd-drm-fixes-6.1-2022-11-16: amdgpu: - Fix a possible memory leak in ganng submit error path - DP tunneling fixes - DCN 3.1 page flip fix - DCN 3.2.x fixes - DCN 3.1.4 fixes - Don't expose degamma on hardware that doesn't support it - BACO fixes for SMU 11.x - BACO fixes for SMU 13.x - Virtual display fix for devices with no display hardware amdkfd: - Memory limit regression fix Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2 parents a73b603 + 4b14841 commit 585f2bc

26 files changed

+235
-69
lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1293,6 +1293,7 @@ void amdgpu_device_pcie_port_wreg(struct amdgpu_device *adev,
12931293
u32 reg, u32 v);
12941294
struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
12951295
struct dma_fence *gang);
1296+
bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev);
12961297

12971298
/* atpx handler */
12981299
#if defined(CONFIG_VGA_SWITCHEROO)

‎drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -171,9 +171,7 @@ int amdgpu_amdkfd_reserve_mem_limit(struct amdgpu_device *adev,
171171
(kfd_mem_limit.ttm_mem_used + ttm_mem_needed >
172172
kfd_mem_limit.max_ttm_mem_limit) ||
173173
(adev && adev->kfd.vram_used + vram_needed >
174-
adev->gmc.real_vram_size -
175-
atomic64_read(&adev->vram_pin_size) -
176-
reserved_for_pt)) {
174+
adev->gmc.real_vram_size - reserved_for_pt)) {
177175
ret = -ENOMEM;
178176
goto release;
179177
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -288,8 +288,10 @@ static int amdgpu_cs_pass1(struct amdgpu_cs_parser *p,
288288
}
289289
}
290290

291-
if (!p->gang_size)
292-
return -EINVAL;
291+
if (!p->gang_size) {
292+
ret = -EINVAL;
293+
goto free_partial_kdata;
294+
}
293295

294296
for (i = 0; i < p->gang_size; ++i) {
295297
ret = amdgpu_job_alloc(p->adev, num_ibs[i], &p->jobs[i], vm);

‎drivers/gpu/drm/amd/amdgpu/amdgpu_device.c

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6044,3 +6044,44 @@ struct dma_fence *amdgpu_device_switch_gang(struct amdgpu_device *adev,
60446044
dma_fence_put(old);
60456045
return NULL;
60466046
}
6047+
6048+
bool amdgpu_device_has_display_hardware(struct amdgpu_device *adev)
6049+
{
6050+
switch (adev->asic_type) {
6051+
#ifdef CONFIG_DRM_AMDGPU_SI
6052+
case CHIP_HAINAN:
6053+
#endif
6054+
case CHIP_TOPAZ:
6055+
/* chips with no display hardware */
6056+
return false;
6057+
#ifdef CONFIG_DRM_AMDGPU_SI
6058+
case CHIP_TAHITI:
6059+
case CHIP_PITCAIRN:
6060+
case CHIP_VERDE:
6061+
case CHIP_OLAND:
6062+
#endif
6063+
#ifdef CONFIG_DRM_AMDGPU_CIK
6064+
case CHIP_BONAIRE:
6065+
case CHIP_HAWAII:
6066+
case CHIP_KAVERI:
6067+
case CHIP_KABINI:
6068+
case CHIP_MULLINS:
6069+
#endif
6070+
case CHIP_TONGA:
6071+
case CHIP_FIJI:
6072+
case CHIP_POLARIS10:
6073+
case CHIP_POLARIS11:
6074+
case CHIP_POLARIS12:
6075+
case CHIP_VEGAM:
6076+
case CHIP_CARRIZO:
6077+
case CHIP_STONEY:
6078+
/* chips with display hardware */
6079+
return true;
6080+
default:
6081+
/* IP discovery */
6082+
if (!adev->ip_versions[DCE_HWIP][0] ||
6083+
(adev->harvest_ip_mask & AMD_HARVEST_IP_DMU_MASK))
6084+
return false;
6085+
return true;
6086+
}
6087+
}

‎drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -656,7 +656,7 @@ void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev)
656656
}
657657

658658
if (amdgpu_sriov_vf(adev) ||
659-
!amdgpu_device_ip_get_ip_block(adev, AMD_IP_BLOCK_TYPE_DCE)) {
659+
!amdgpu_device_has_display_hardware(adev)) {
660660
size = 0;
661661
} else {
662662
size = amdgpu_gmc_get_vbios_fb_size(adev);

‎drivers/gpu/drm/amd/amdgpu/psp_v13_0.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -45,6 +45,7 @@ MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
4545
MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
4646
MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
4747
MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");
48+
MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin");
4849

4950
/* For large FW files the time to complete can be very long */
5051
#define USBC_PD_POLLING_LIMIT_S 240

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

Lines changed: 26 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -147,6 +147,14 @@ MODULE_FIRMWARE(FIRMWARE_NAVI12_DMCU);
147147
/* Number of bytes in PSP footer for firmware. */
148148
#define PSP_FOOTER_BYTES 0x100
149149

150+
/*
151+
* DMUB Async to Sync Mechanism Status
152+
*/
153+
#define DMUB_ASYNC_TO_SYNC_ACCESS_FAIL 1
154+
#define DMUB_ASYNC_TO_SYNC_ACCESS_TIMEOUT 2
155+
#define DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS 3
156+
#define DMUB_ASYNC_TO_SYNC_ACCESS_INVALID 4
157+
150158
/**
151159
* DOC: overview
152160
*
@@ -1637,19 +1645,19 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
16371645
}
16381646
}
16391647

1640-
if (amdgpu_dm_initialize_drm_device(adev)) {
1641-
DRM_ERROR(
1642-
"amdgpu: failed to initialize sw for display support.\n");
1643-
goto error;
1644-
}
1645-
16461648
/* Enable outbox notification only after IRQ handlers are registered and DMUB is alive.
16471649
* It is expected that DMUB will resend any pending notifications at this point, for
16481650
* example HPD from DPIA.
16491651
*/
16501652
if (dc_is_dmub_outbox_supported(adev->dm.dc))
16511653
dc_enable_dmub_outbox(adev->dm.dc);
16521654

1655+
if (amdgpu_dm_initialize_drm_device(adev)) {
1656+
DRM_ERROR(
1657+
"amdgpu: failed to initialize sw for display support.\n");
1658+
goto error;
1659+
}
1660+
16531661
/* create fake encoders for MST */
16541662
dm_dp_create_fake_mst_encoders(adev);
16551663

@@ -10109,6 +10117,8 @@ static int amdgpu_dm_set_dmub_async_sync_status(bool is_cmd_aux,
1010910117
*operation_result = AUX_RET_ERROR_TIMEOUT;
1011010118
} else if (status_type == DMUB_ASYNC_TO_SYNC_ACCESS_FAIL) {
1011110119
*operation_result = AUX_RET_ERROR_ENGINE_ACQUIRE;
10120+
} else if (status_type == DMUB_ASYNC_TO_SYNC_ACCESS_INVALID) {
10121+
*operation_result = AUX_RET_ERROR_INVALID_REPLY;
1011210122
} else {
1011310123
*operation_result = AUX_RET_ERROR_UNKNOWN;
1011410124
}
@@ -10156,6 +10166,16 @@ int amdgpu_dm_process_dmub_aux_transfer_sync(bool is_cmd_aux, struct dc_context
1015610166
payload->reply[0] = adev->dm.dmub_notify->aux_reply.command;
1015710167
if (!payload->write && adev->dm.dmub_notify->aux_reply.length &&
1015810168
payload->reply[0] == AUX_TRANSACTION_REPLY_AUX_ACK) {
10169+
10170+
if (payload->length != adev->dm.dmub_notify->aux_reply.length) {
10171+
DRM_WARN("invalid read from DPIA AUX %x(%d) got length %d!\n",
10172+
payload->address, payload->length,
10173+
adev->dm.dmub_notify->aux_reply.length);
10174+
return amdgpu_dm_set_dmub_async_sync_status(is_cmd_aux, ctx,
10175+
DMUB_ASYNC_TO_SYNC_ACCESS_INVALID,
10176+
(uint32_t *)operation_result);
10177+
}
10178+
1015910179
memcpy(payload->data, adev->dm.dmub_notify->aux_reply.data,
1016010180
adev->dm.dmub_notify->aux_reply.length);
1016110181
}

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -50,12 +50,6 @@
5050

5151
#define AMDGPU_DMUB_NOTIFICATION_MAX 5
5252

53-
/*
54-
* DMUB Async to Sync Mechanism Status
55-
*/
56-
#define DMUB_ASYNC_TO_SYNC_ACCESS_FAIL 1
57-
#define DMUB_ASYNC_TO_SYNC_ACCESS_TIMEOUT 2
58-
#define DMUB_ASYNC_TO_SYNC_ACCESS_SUCCESS 3
5953
/*
6054
#include "include/amdgpu_dal_power_if.h"
6155
#include "amdgpu_dm_irq.h"

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crtc.c

Lines changed: 8 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -412,7 +412,7 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
412412
{
413413
struct amdgpu_crtc *acrtc = NULL;
414414
struct drm_plane *cursor_plane;
415-
415+
bool is_dcn;
416416
int res = -ENOMEM;
417417

418418
cursor_plane = kzalloc(sizeof(*cursor_plane), GFP_KERNEL);
@@ -450,8 +450,14 @@ int amdgpu_dm_crtc_init(struct amdgpu_display_manager *dm,
450450
acrtc->otg_inst = -1;
451451

452452
dm->adev->mode_info.crtcs[crtc_index] = acrtc;
453-
drm_crtc_enable_color_mgmt(&acrtc->base, MAX_COLOR_LUT_ENTRIES,
453+
454+
/* Don't enable DRM CRTC degamma property for DCE since it doesn't
455+
* support programmable degamma anywhere.
456+
*/
457+
is_dcn = dm->adev->dm.dc->caps.color.dpp.dcn_arch;
458+
drm_crtc_enable_color_mgmt(&acrtc->base, is_dcn ? MAX_COLOR_LUT_ENTRIES : 0,
454459
true, MAX_COLOR_LUT_ENTRIES);
460+
455461
drm_mode_crtc_set_gamma_size(&acrtc->base, MAX_COLOR_LEGACY_LUT_ENTRIES);
456462

457463
return 0;

‎drivers/gpu/drm/amd/display/dc/bios/bios_parser2.c

Lines changed: 30 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2393,6 +2393,26 @@ static enum bp_result get_vram_info_v25(
23932393
return result;
23942394
}
23952395

2396+
static enum bp_result get_vram_info_v30(
2397+
struct bios_parser *bp,
2398+
struct dc_vram_info *info)
2399+
{
2400+
struct atom_vram_info_header_v3_0 *info_v30;
2401+
enum bp_result result = BP_RESULT_OK;
2402+
2403+
info_v30 = GET_IMAGE(struct atom_vram_info_header_v3_0,
2404+
DATA_TABLES(vram_info));
2405+
2406+
if (info_v30 == NULL)
2407+
return BP_RESULT_BADBIOSTABLE;
2408+
2409+
info->num_chans = info_v30->channel_num;
2410+
info->dram_channel_width_bytes = (1 << info_v30->channel_width) / 8;
2411+
2412+
return result;
2413+
}
2414+
2415+
23962416
/*
23972417
* get_integrated_info_v11
23982418
*
@@ -3060,6 +3080,16 @@ static enum bp_result bios_parser_get_vram_info(
30603080
}
30613081
break;
30623082

3083+
case 3:
3084+
switch (revision.minor) {
3085+
case 0:
3086+
result = get_vram_info_v30(bp, info);
3087+
break;
3088+
default:
3089+
break;
3090+
}
3091+
break;
3092+
30633093
default:
30643094
return result;
30653095
}

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