@@ -53,16 +53,17 @@ struct vt8500_chip {
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#define to_vt8500_chip (chip ) container_of(chip, struct vt8500_chip, chip)
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#define msecs_to_loops (t ) (loops_per_jiffy / 1000 * HZ * t)
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- static inline void vt8500_pwm_busy_wait (struct vt8500_chip * vt8500 , int nr , u8 bitmask )
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+ static inline void vt8500_pwm_busy_wait (struct pwm_chip * chip , int nr , u8 bitmask )
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{
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+ struct vt8500_chip * vt8500 = to_vt8500_chip (chip );
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int loops = msecs_to_loops (10 );
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u32 mask = bitmask << (nr << 8 );
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while ((readl (vt8500 -> base + REG_STATUS ) & mask ) && -- loops )
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cpu_relax ();
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if (unlikely (!loops ))
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- dev_warn (vt8500 -> chip . dev , "Waiting for status bits 0x%x to clear timed out\n" ,
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+ dev_warn (chip -> dev , "Waiting for status bits 0x%x to clear timed out\n" ,
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mask );
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}
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@@ -103,18 +104,18 @@ static int vt8500_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm,
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dc = div64_u64 (c , period_ns );
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writel (prescale , vt8500 -> base + REG_SCALAR (pwm -> hwpwm ));
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- vt8500_pwm_busy_wait (vt8500 , pwm -> hwpwm , STATUS_SCALAR_UPDATE );
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+ vt8500_pwm_busy_wait (chip , pwm -> hwpwm , STATUS_SCALAR_UPDATE );
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writel (pv , vt8500 -> base + REG_PERIOD (pwm -> hwpwm ));
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- vt8500_pwm_busy_wait (vt8500 , pwm -> hwpwm , STATUS_PERIOD_UPDATE );
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+ vt8500_pwm_busy_wait (chip , pwm -> hwpwm , STATUS_PERIOD_UPDATE );
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writel (dc , vt8500 -> base + REG_DUTY (pwm -> hwpwm ));
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- vt8500_pwm_busy_wait (vt8500 , pwm -> hwpwm , STATUS_DUTY_UPDATE );
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+ vt8500_pwm_busy_wait (chip , pwm -> hwpwm , STATUS_DUTY_UPDATE );
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val = readl (vt8500 -> base + REG_CTRL (pwm -> hwpwm ));
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val |= CTRL_AUTOLOAD ;
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writel (val , vt8500 -> base + REG_CTRL (pwm -> hwpwm ));
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- vt8500_pwm_busy_wait (vt8500 , pwm -> hwpwm , STATUS_CTRL_UPDATE );
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+ vt8500_pwm_busy_wait (chip , pwm -> hwpwm , STATUS_CTRL_UPDATE );
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clk_disable (vt8500 -> clk );
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return 0 ;
@@ -135,7 +136,7 @@ static int vt8500_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
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val = readl (vt8500 -> base + REG_CTRL (pwm -> hwpwm ));
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val |= CTRL_ENABLE ;
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writel (val , vt8500 -> base + REG_CTRL (pwm -> hwpwm ));
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- vt8500_pwm_busy_wait (vt8500 , pwm -> hwpwm , STATUS_CTRL_UPDATE );
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+ vt8500_pwm_busy_wait (chip , pwm -> hwpwm , STATUS_CTRL_UPDATE );
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return 0 ;
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}
@@ -148,7 +149,7 @@ static void vt8500_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
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val = readl (vt8500 -> base + REG_CTRL (pwm -> hwpwm ));
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val &= ~CTRL_ENABLE ;
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writel (val , vt8500 -> base + REG_CTRL (pwm -> hwpwm ));
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- vt8500_pwm_busy_wait (vt8500 , pwm -> hwpwm , STATUS_CTRL_UPDATE );
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+ vt8500_pwm_busy_wait (chip , pwm -> hwpwm , STATUS_CTRL_UPDATE );
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clk_disable (vt8500 -> clk );
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}
@@ -168,7 +169,7 @@ static int vt8500_pwm_set_polarity(struct pwm_chip *chip,
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val &= ~CTRL_INVERT ;
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writel (val , vt8500 -> base + REG_CTRL (pwm -> hwpwm ));
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- vt8500_pwm_busy_wait (vt8500 , pwm -> hwpwm , STATUS_CTRL_UPDATE );
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+ vt8500_pwm_busy_wait (chip , pwm -> hwpwm , STATUS_CTRL_UPDATE );
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return 0 ;
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}
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