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| 1 | +// SPDX-License-Identifier: GPL-2.0-only OR MIT |
| 2 | +/** |
| 3 | + * DT Overlay for enabling PCIE1 instance in Endpoint Configuration with the |
| 4 | + * AM68-SK board. |
| 5 | + * |
| 6 | + * AM68-SK Board Product Link: https://www.ti.com/tool/SK-AM68 |
| 7 | + * |
| 8 | + * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/ |
| 9 | + */ |
| 10 | + |
| 11 | +/dts-v1/; |
| 12 | +/plugin/; |
| 13 | + |
| 14 | +#include <dt-bindings/interrupt-controller/arm-gic.h> |
| 15 | +#include <dt-bindings/soc/ti,sci_pm_domain.h> |
| 16 | + |
| 17 | +#include "k3-pinctrl.h" |
| 18 | + |
| 19 | +/* |
| 20 | + * Since Root Complex and Endpoint modes are mutually exclusive |
| 21 | + * disable Root Complex mode. |
| 22 | + */ |
| 23 | +&pcie1_rc { |
| 24 | + status = "disabled"; |
| 25 | +}; |
| 26 | + |
| 27 | +&cbass_main { |
| 28 | + #address-cells = <2>; |
| 29 | + #size-cells = <2>; |
| 30 | + interrupt-parent = <&gic500>; |
| 31 | + |
| 32 | + pcie1_ep: pcie-ep@2910000 { |
| 33 | + compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep"; |
| 34 | + reg = <0x00 0x02910000 0x00 0x1000>, |
| 35 | + <0x00 0x02917000 0x00 0x400>, |
| 36 | + <0x00 0x0d800000 0x00 0x00800000>, |
| 37 | + <0x00 0x18000000 0x00 0x08000000>; |
| 38 | + reg-names = "intd_cfg", "user_cfg", "reg", "mem"; |
| 39 | + interrupt-names = "link_state"; |
| 40 | + interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>; |
| 41 | + max-link-speed = <3>; |
| 42 | + num-lanes = <2>; |
| 43 | + power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>; |
| 44 | + clocks = <&k3_clks 276 41>; |
| 45 | + clock-names = "fck"; |
| 46 | + max-functions = /bits/ 8 <6>; |
| 47 | + max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>; |
| 48 | + dma-coherent; |
| 49 | + phys = <&serdes0_pcie_link>; |
| 50 | + phy-names = "pcie-phy"; |
| 51 | + ti,syscon-pcie-ctrl = <&scm_conf 0x074>; |
| 52 | + }; |
| 53 | +}; |
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