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Merge tag 'samsung-clk-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung
Pull Samsung clk driver updates from Krzysztof Kozlowski: - Re-add support for Exynos4212 clock controller because we are re-introducing the SoC in the mainline - Add CONFIG_OF dependency to solve some objtool warnings * tag 'samsung-clk-6.5' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux: clk: samsung: add CONFIG_OF dependency clk: samsung: Re-add support for Exynos4212 CPU clock clk: samsung: Add Exynos4212 compatible to CLKOUT driver dt-bindings: clock: samsung,exynos: add Exynos4212 clock compatible
2 parents ac9a786 + 2aac2d8 commit 59374d0

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‎Documentation/devicetree/bindings/clock/samsung,exynos-clock.yaml

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Original file line numberDiff line numberDiff line change
@@ -24,6 +24,7 @@ properties:
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- samsung,exynos3250-cmu-dmc
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- samsung,exynos3250-cmu-isp
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- samsung,exynos4210-clock
27+
- samsung,exynos4212-clock
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- samsung,exynos4412-clock
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- samsung,exynos5250-clock
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- items:

‎drivers/clk/samsung/Kconfig

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Original file line numberDiff line numberDiff line change
@@ -2,6 +2,7 @@
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# Recent Exynos platforms should just select COMMON_CLK_SAMSUNG:
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config COMMON_CLK_SAMSUNG
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bool "Samsung Exynos clock controller support" if COMPILE_TEST
5+
depends on OF
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select S3C64XX_COMMON_CLK if ARM && ARCH_S3C64XX
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select S5PV210_COMMON_CLK if ARM && ARCH_S5PV210
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select EXYNOS_3250_COMMON_CLK if ARM && SOC_EXYNOS3250

‎drivers/clk/samsung/clk-exynos-clkout.c

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Original file line numberDiff line numberDiff line change
@@ -55,6 +55,9 @@ static const struct of_device_id exynos_clkout_ids[] = {
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}, {
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.compatible = "samsung,exynos4210-pmu",
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.data = &exynos_clkout_exynos4,
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}, {
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.compatible = "samsung,exynos4212-pmu",
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.data = &exynos_clkout_exynos4,
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}, {
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.compatible = "samsung,exynos4412-pmu",
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.data = &exynos_clkout_exynos4,

‎drivers/clk/samsung/clk-exynos4.c

Lines changed: 39 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -138,7 +138,8 @@
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/* the exynos4 soc type */
139139
enum exynos4_soc {
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EXYNOS4210,
141-
EXYNOS4X12,
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EXYNOS4212,
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EXYNOS4412,
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};
143144

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/* list of PLLs to be registered */
@@ -1205,6 +1206,24 @@ static const struct exynos_cpuclk_cfg_data e4210_armclk_d[] __initconst = {
12051206
{ 0 },
12061207
};
12071208

1209+
static const struct exynos_cpuclk_cfg_data e4212_armclk_d[] __initconst = {
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{ 1500000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
1211+
{ 1400000, E4210_CPU_DIV0(2, 1, 6, 0, 7, 3), E4210_CPU_DIV1(2, 6), },
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{ 1300000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
1213+
{ 1200000, E4210_CPU_DIV0(2, 1, 5, 0, 7, 3), E4210_CPU_DIV1(2, 5), },
1214+
{ 1100000, E4210_CPU_DIV0(2, 1, 4, 0, 6, 3), E4210_CPU_DIV1(2, 4), },
1215+
{ 1000000, E4210_CPU_DIV0(1, 1, 4, 0, 5, 2), E4210_CPU_DIV1(2, 4), },
1216+
{ 900000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
1217+
{ 800000, E4210_CPU_DIV0(1, 1, 3, 0, 5, 2), E4210_CPU_DIV1(2, 3), },
1218+
{ 700000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
1219+
{ 600000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
1220+
{ 500000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
1221+
{ 400000, E4210_CPU_DIV0(1, 1, 3, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
1222+
{ 300000, E4210_CPU_DIV0(1, 1, 2, 0, 4, 2), E4210_CPU_DIV1(2, 3), },
1223+
{ 200000, E4210_CPU_DIV0(1, 1, 1, 0, 3, 1), E4210_CPU_DIV1(2, 3), },
1224+
{ 0 },
1225+
};
1226+
12081227
#define E4412_CPU_DIV1(cores, hpm, copy) \
12091228
(((cores) << 8) | ((hpm) << 4) | ((copy) << 0))
12101229

@@ -1233,6 +1252,11 @@ static const struct samsung_cpu_clock exynos4210_cpu_clks[] __initconst = {
12331252
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4210_armclk_d),
12341253
};
12351254

1255+
static const struct samsung_cpu_clock exynos4212_cpu_clks[] __initconst = {
1256+
CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
1257+
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4212_armclk_d),
1258+
};
1259+
12361260
static const struct samsung_cpu_clock exynos4412_cpu_clks[] __initconst = {
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CPU_CLK(CLK_ARM_CLK, "armclk", CLK_MOUT_APLL, CLK_MOUT_MPLL_USER_C,
12381262
CLK_CPU_NEEDS_DEBUG_ALT_DIV | CLK_CPU_HAS_DIV1, 0x14200, e4412_armclk_d),
@@ -1326,11 +1350,15 @@ static void __init exynos4_clk_init(struct device_node *np,
13261350
samsung_clk_register_fixed_factor(ctx,
13271351
exynos4x12_fixed_factor_clks,
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ARRAY_SIZE(exynos4x12_fixed_factor_clks));
1329-
samsung_clk_register_cpu(ctx, exynos4412_cpu_clks,
1330-
ARRAY_SIZE(exynos4412_cpu_clks));
1353+
if (soc == EXYNOS4412)
1354+
samsung_clk_register_cpu(ctx, exynos4412_cpu_clks,
1355+
ARRAY_SIZE(exynos4412_cpu_clks));
1356+
else
1357+
samsung_clk_register_cpu(ctx, exynos4212_cpu_clks,
1358+
ARRAY_SIZE(exynos4212_cpu_clks));
13311359
}
13321360

1333-
if (soc == EXYNOS4X12)
1361+
if (soc == EXYNOS4212 || soc == EXYNOS4412)
13341362
exynos4x12_core_down_clock();
13351363

13361364
samsung_clk_extended_sleep_init(reg_base,
@@ -1363,8 +1391,14 @@ static void __init exynos4210_clk_init(struct device_node *np)
13631391
}
13641392
CLK_OF_DECLARE(exynos4210_clk, "samsung,exynos4210-clock", exynos4210_clk_init);
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1394+
static void __init exynos4212_clk_init(struct device_node *np)
1395+
{
1396+
exynos4_clk_init(np, EXYNOS4212);
1397+
}
1398+
CLK_OF_DECLARE(exynos4212_clk, "samsung,exynos4212-clock", exynos4212_clk_init);
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static void __init exynos4412_clk_init(struct device_node *np)
13671401
{
1368-
exynos4_clk_init(np, EXYNOS4X12);
1402+
exynos4_clk_init(np, EXYNOS4412);
13691403
}
13701404
CLK_OF_DECLARE(exynos4412_clk, "samsung,exynos4412-clock", exynos4412_clk_init);

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