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Hsiao Chien SungChun-Kuang Hu
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drm/mediatek: Support "Pre-multiplied" blending in Mixer
Support "Pre-multiplied" alpha blending mode in Mixer. Before this patch, only the coverage mode is supported. To replace the default setting that is set in mtk_ethdr_config(), we change mtk_ddp_write_mask() to mtk_ddp_write(), and this change will also reset the NON_PREMULTI_SOURCE bit that was assigned in mtk_ethdr_config(). Therefore, we must still set NON_PREMULTI_SOURCE bit if the blend mode is not DRM_MODE_BLEND_PREMULTI. Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Signed-off-by: Hsiao Chien Sung <[email protected]> Reviewed-by: CK Hu <[email protected]> Link: https://patchwork.kernel.org/project/dri-devel/patch/[email protected]/ Signed-off-by: Chun-Kuang Hu <[email protected]>
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drivers/gpu/drm/mediatek/mtk_ethdr.c

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -36,6 +36,7 @@
3636
#define MIX_SRC_L0_EN BIT(0)
3737
#define MIX_L_SRC_CON(n) (0x28 + 0x18 * (n))
3838
#define NON_PREMULTI_SOURCE (2 << 12)
39+
#define PREMULTI_SOURCE (3 << 12)
3940
#define MIX_L_SRC_SIZE(n) (0x30 + 0x18 * (n))
4041
#define MIX_L_SRC_OFFSET(n) (0x34 + 0x18 * (n))
4142
#define MIX_FUNC_DCM0 0x120
@@ -176,6 +177,11 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
176177
alpha_con |= state->base.alpha & MIXER_ALPHA;
177178
}
178179

180+
if (state->base.pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
181+
alpha_con |= PREMULTI_SOURCE;
182+
else
183+
alpha_con |= NON_PREMULTI_SOURCE;
184+
179185
if ((state->base.fb && !state->base.fb->format->has_alpha) ||
180186
state->base.pixel_blend_mode == DRM_MODE_BLEND_PIXEL_NONE) {
181187
/*
@@ -193,8 +199,7 @@ void mtk_ethdr_layer_config(struct device *dev, unsigned int idx,
193199
mtk_ddp_write(cmdq_pkt, pending->height << 16 | align_width, &mixer->cmdq_base,
194200
mixer->regs, MIX_L_SRC_SIZE(idx));
195201
mtk_ddp_write(cmdq_pkt, offset, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_OFFSET(idx));
196-
mtk_ddp_write_mask(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx),
197-
0x1ff);
202+
mtk_ddp_write(cmdq_pkt, alpha_con, &mixer->cmdq_base, mixer->regs, MIX_L_SRC_CON(idx));
198203
mtk_ddp_write_mask(cmdq_pkt, BIT(idx), &mixer->cmdq_base, mixer->regs, MIX_SRC_CON,
199204
BIT(idx));
200205
}

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