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13 | 13 | struct xapic_vcpu {
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14 | 14 | struct kvm_vcpu *vcpu;
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15 | 15 | bool is_x2apic;
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| 16 | + bool has_xavic_errata; |
16 | 17 | };
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17 | 18 |
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18 | 19 | static void xapic_guest_code(void)
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@@ -79,12 +80,17 @@ static void ____test_icr(struct xapic_vcpu *x, uint64_t val)
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79 | 80 | vcpu_ioctl(vcpu, KVM_GET_LAPIC, &xapic);
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80 | 81 | icr = (u64)(*((u32 *)&xapic.regs[APIC_ICR])) |
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81 | 82 | (u64)(*((u32 *)&xapic.regs[APIC_ICR2])) << 32;
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82 |
| - if (!x->is_x2apic) |
83 |
| - val &= (-1u | (0xffull << (32 + 24))); |
84 |
| - else if (val & X2APIC_RSVD_BITS_MASK) |
| 83 | + if (!x->is_x2apic) { |
| 84 | + if (!x->has_xavic_errata) |
| 85 | + val &= (-1u | (0xffull << (32 + 24))); |
| 86 | + } else if (val & X2APIC_RSVD_BITS_MASK) { |
85 | 87 | return;
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| 88 | + } |
86 | 89 |
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87 |
| - TEST_ASSERT_EQ(icr, val & ~APIC_ICR_BUSY); |
| 90 | + if (x->has_xavic_errata) |
| 91 | + TEST_ASSERT_EQ(icr & ~APIC_ICR_BUSY, val & ~APIC_ICR_BUSY); |
| 92 | + else |
| 93 | + TEST_ASSERT_EQ(icr, val & ~APIC_ICR_BUSY); |
88 | 94 | }
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89 | 95 |
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90 | 96 | static void __test_icr(struct xapic_vcpu *x, uint64_t val)
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@@ -236,6 +242,15 @@ int main(int argc, char *argv[])
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236 | 242 | vm = vm_create_with_one_vcpu(&x.vcpu, xapic_guest_code);
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237 | 243 | x.is_x2apic = false;
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238 | 244 |
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| 245 | + /* |
| 246 | + * AMD's AVIC implementation is buggy (fails to clear the ICR BUSY bit), |
| 247 | + * and also diverges from KVM with respect to ICR2[23:0] (KVM and Intel |
| 248 | + * drops writes, AMD does not). Account for the errata when checking |
| 249 | + * that KVM reads back what was written. |
| 250 | + */ |
| 251 | + x.has_xavic_errata = host_cpu_is_amd && |
| 252 | + get_kvm_amd_param_bool("avic"); |
| 253 | + |
239 | 254 | vcpu_clear_cpuid_feature(x.vcpu, X86_FEATURE_X2APIC);
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240 | 255 |
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241 | 256 | virt_pg_map(vm, APIC_DEFAULT_GPA, APIC_DEFAULT_GPA);
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