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perf vendor events amd: Add Zen 4 uncore events
Add uncore events taken from Section 2.1.15.5 "L3 Cache Performance Monitor Counter"s and Section 7.1 "Fabric Performance Monitor Counter (PMC) Events" in the Processor Programming Reference (PPR) for AMD Family 19h Model 11h Revision B1 processors. This constitutes events which capture L3 cache activity and data bandwidth for various links and interfaces in the Data Fabric. Signed-off-by: Sandipan Das <[email protected]> Acked-by: Ian Rogers <[email protected]> Cc: Alexander Shishkin <[email protected]> Cc: Ananth Narayan <[email protected]> Cc: Ingo Molnar <[email protected]> Cc: Jiri Olsa <[email protected]> Cc: Jirka Hladky <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Namhyung Kim <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Ravi Bangoria <[email protected]> Cc: Stephane Eranian <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnaldo Carvalho de Melo <[email protected]>
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tools/perf/pmu-events/arch/x86/amdzen4/cache.json

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"EventCode": "0x28f",
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"BriefDescription": "Op cache accesses of all types.",
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"UMask": "0x07"
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},
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{
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"EventName": "l3_lookup_state.l3_miss",
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"EventCode": "0x04",
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"BriefDescription": "L3 cache misses.",
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"UMask": "0x01",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_lookup_state.l3_hit",
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"EventCode": "0x04",
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"BriefDescription": "L3 cache hits.",
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"UMask": "0xfe",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_lookup_state.all_coherent_accesses_to_l3",
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"EventCode": "0x04",
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"BriefDescription": "L3 cache requests for all coherent accesses.",
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"UMask": "0xff",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.dram_near",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency when data is sourced from DRAM in the same NUMA node.",
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"UMask": "0x01",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.dram_far",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency when data is sourced from DRAM in a different NUMA node.",
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"UMask": "0x02",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.near_cache",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in the same NUMA node.",
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"UMask": "0x04",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.far_cache",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency when data is sourced from another CCX's cache when the address was in a different NUMA node.",
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"UMask": "0x08",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.ext_near",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in the same NUMA node.",
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"UMask": "0x10",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.ext_far",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency when data is sourced from extension memory (CXL) in a different NUMA node.",
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"UMask": "0x20",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency.all",
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"EventCode": "0xac",
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"BriefDescription": "Average sampled latency from all data sources.",
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"UMask": "0x3f",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.dram_near",
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"EventCode": "0xad",
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"BriefDescription": "L3 cache fill requests sourced from DRAM in the same NUMA node.",
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"UMask": "0x01",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.dram_far",
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"EventCode": "0xad",
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"BriefDescription": "L3 cache fill requests sourced from DRAM in a different NUMA node.",
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"UMask": "0x02",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.near_cache",
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"EventCode": "0xad",
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"BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in the same NUMA node.",
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"UMask": "0x04",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.far_cache",
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"EventCode": "0xad",
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"BriefDescription": "L3 cache fill requests sourced from another CCX's cache when the address was in a different NUMA node.",
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"UMask": "0x08",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.ext_near",
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"EventCode": "0xad",
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"BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in the same NUMA node.",
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"UMask": "0x10",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.ext_far",
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"EventCode": "0xad",
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"BriefDescription": "L3 cache fill requests sourced from extension memory (CXL) in a different NUMA node.",
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"UMask": "0x20",
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"Unit": "L3PMC"
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},
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{
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"EventName": "l3_xi_sampled_latency_requests.all",
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"EventCode": "0xad",
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"BriefDescription": "L3 cache fill requests sourced from all data sources.",
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"UMask": "0x3f",
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"Unit": "L3PMC"
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}
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]

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