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165 | 165 | mrs x1, id_aa64dfr0_el1
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166 | 166 | ubfx x1, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4
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167 | 167 | cmp x1, #3
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168 |
| - b.lt .Lset_debug_fgt_\@ |
| 168 | + b.lt .Lskip_spe_fgt_\@ |
169 | 169 | /* Disable PMSNEVFR_EL1 read and write traps */
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170 | 170 | orr x0, x0, #(1 << 62)
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171 | 171 |
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172 |
| -.Lset_debug_fgt_\@: |
| 172 | +.Lskip_spe_fgt_\@: |
173 | 173 | msr_s SYS_HDFGRTR_EL2, x0
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174 | 174 | msr_s SYS_HDFGWTR_EL2, x0
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175 | 175 |
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176 | 176 | mov x0, xzr
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177 | 177 | mrs x1, id_aa64pfr1_el1
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178 | 178 | ubfx x1, x1, #ID_AA64PFR1_EL1_SME_SHIFT, #4
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179 |
| - cbz x1, .Lset_pie_fgt_\@ |
| 179 | + cbz x1, .Lskip_debug_fgt_\@ |
180 | 180 |
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181 | 181 | /* Disable nVHE traps of TPIDR2 and SMPRI */
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182 | 182 | orr x0, x0, #HFGxTR_EL2_nSMPRI_EL1_MASK
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183 | 183 | orr x0, x0, #HFGxTR_EL2_nTPIDR2_EL0_MASK
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184 | 184 |
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185 |
| -.Lset_pie_fgt_\@: |
| 185 | +.Lskip_debug_fgt_\@: |
186 | 186 | mrs_s x1, SYS_ID_AA64MMFR3_EL1
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187 | 187 | ubfx x1, x1, #ID_AA64MMFR3_EL1_S1PIE_SHIFT, #4
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188 |
| - cbz x1, .Lset_fgt_\@ |
| 188 | + cbz x1, .Lskip_pie_fgt_\@ |
189 | 189 |
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190 | 190 | /* Disable trapping of PIR_EL1 / PIRE0_EL1 */
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191 | 191 | orr x0, x0, #HFGxTR_EL2_nPIR_EL1
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192 | 192 | orr x0, x0, #HFGxTR_EL2_nPIRE0_EL1
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193 | 193 |
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194 |
| -.Lset_fgt_\@: |
| 194 | +.Lskip_pie_fgt_\@: |
195 | 195 | msr_s SYS_HFGRTR_EL2, x0
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196 | 196 | msr_s SYS_HFGWTR_EL2, x0
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197 | 197 | msr_s SYS_HFGITR_EL2, xzr
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198 | 198 |
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199 | 199 | mrs x1, id_aa64pfr0_el1 // AMU traps UNDEF without AMU
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200 | 200 | ubfx x1, x1, #ID_AA64PFR0_EL1_AMU_SHIFT, #4
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201 |
| - cbz x1, .Lskip_fgt_\@ |
| 201 | + cbz x1, .Lskip_amu_fgt_\@ |
202 | 202 |
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203 | 203 | msr_s SYS_HAFGRTR_EL2, xzr
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| 204 | + |
| 205 | +.Lskip_amu_fgt_\@: |
| 206 | + |
204 | 207 | .Lskip_fgt_\@:
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205 | 208 | .endm
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206 | 209 |
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