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Merge tag 'omap-for-v5.8/fixes-merge-window-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/fixes
Fixes for omaps for v5.8 The recent display subsystem (DSS) related platform data changes caused display related regressions for suspend and resume. Looks like I only tested suspend and resume before dropping the legacy platform data, and forgot to test it after dropping it. Turns out the main issue was that we no longer have platform code calling pm_runtime_suspend for DSS like we did for the legacy platform data case, and that fix is still being discussed on the dri-devel list and will get merged separately. The DSS related testing exposed a pile other other display related issues that also need fixing though: - Fix ti-sysc optional clock handling and reset status checks for devices that reset automatically in idle like DSS - Ignore ti-sysc clockactivity bit unless separately requested to avoid unexpected performance issues - Init ti-sysc framedonetv_irq to true and disable for am4 - Avoid duplicate DSS reset for legacy mode with dts data - Remove LCD timings for am4 as they cause warnings now that we're using generic panels Then there is a pile of other fixes not related to the DSS: - Fix omap_prm reset deassert as we still have drivers setting the pm_runtime_irq_safe() flag - Flush posted write for ti-sysc enable and disable - Fix droid4 spi related errors with spi flags - Fix am335x USB range and a typo for softreset - Fix dra7 timer nodes for clocks for IPU and DSP - Drop duplicate mailboxes after mismerge for dra7 * tag 'omap-for-v5.8/fixes-merge-window-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: Revert "bus: ti-sysc: Increase max softreset wait" ARM: dts: am437x-epos-evm: remove lcd timings ARM: dts: am437x-gp-evm: remove lcd timings ARM: dts: am437x-sk-evm: remove lcd timings ARM: dts: dra7-evm-common: Fix duplicate mailbox nodes ARM: dts: dra7: Fix timer nodes properly for timer_sys_ck clocks ARM: dts: Fix am33xx.dtsi ti,sysc-mask wrong softreset flag ARM: dts: Fix am33xx.dtsi USB ranges length bus: ti-sysc: Increase max softreset wait ARM: OMAP2+: Fix legacy mode dss_reset bus: ti-sysc: Fix uninitialized framedonetv_irq bus: ti-sysc: Ignore clockactivity unless specified as a quirk bus: ti-sysc: Use optional clocks on for enable and wait for softreset bit ARM: dts: omap4-droid4: Fix spi configuration and increase rate bus: ti-sysc: Flush posted write on enable and disable soc: ti: omap-prm: use atomic iopoll instead of sleeping one Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Arnd Bergmann <[email protected]>
2 parents 4877846 + e4a8fc0 commit 5b75f16

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‎arch/arm/boot/dts/am33xx.dtsi

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -335,7 +335,7 @@
335335
<0x47400010 0x4>;
336336
reg-names = "rev", "sysc";
337337
ti,sysc-mask = <(SYSC_OMAP4_FREEEMU |
338-
SYSC_OMAP2_SOFTRESET)>;
338+
SYSC_OMAP4_SOFTRESET)>;
339339
ti,sysc-midle = <SYSC_IDLE_FORCE>,
340340
<SYSC_IDLE_NO>,
341341
<SYSC_IDLE_SMART>;
@@ -347,7 +347,7 @@
347347
clock-names = "fck";
348348
#address-cells = <1>;
349349
#size-cells = <1>;
350-
ranges = <0x0 0x47400000 0x5000>;
350+
ranges = <0x0 0x47400000 0x8000>;
351351

352352
usb0_phy: usb-phy@1300 {
353353
compatible = "ti,am335x-usb-phy";

‎arch/arm/boot/dts/am437x-gp-evm.dts

Lines changed: 0 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -91,22 +91,6 @@
9191

9292
backlight = <&lcd_bl>;
9393

94-
panel-timing {
95-
clock-frequency = <33000000>;
96-
hactive = <800>;
97-
vactive = <480>;
98-
hfront-porch = <210>;
99-
hback-porch = <16>;
100-
hsync-len = <30>;
101-
vback-porch = <10>;
102-
vfront-porch = <22>;
103-
vsync-len = <13>;
104-
hsync-active = <0>;
105-
vsync-active = <0>;
106-
de-active = <1>;
107-
pixelclk-active = <1>;
108-
};
109-
11094
port {
11195
lcd_in: endpoint {
11296
remote-endpoint = <&dpi_out>;

‎arch/arm/boot/dts/am437x-sk-evm.dts

Lines changed: 0 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -134,22 +134,6 @@
134134

135135
enable-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
136136

137-
panel-timing {
138-
clock-frequency = <9000000>;
139-
hactive = <480>;
140-
vactive = <272>;
141-
hfront-porch = <2>;
142-
hback-porch = <2>;
143-
hsync-len = <41>;
144-
vfront-porch = <2>;
145-
vback-porch = <2>;
146-
vsync-len = <10>;
147-
hsync-active = <0>;
148-
vsync-active = <0>;
149-
de-active = <1>;
150-
pixelclk-active = <1>;
151-
};
152-
153137
port {
154138
lcd_in: endpoint {
155139
remote-endpoint = <&dpi_out>;

‎arch/arm/boot/dts/am43x-epos-evm.dts

Lines changed: 0 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -47,22 +47,6 @@
4747

4848
backlight = <&lcd_bl>;
4949

50-
panel-timing {
51-
clock-frequency = <33000000>;
52-
hactive = <800>;
53-
vactive = <480>;
54-
hfront-porch = <210>;
55-
hback-porch = <16>;
56-
hsync-len = <30>;
57-
vback-porch = <10>;
58-
vfront-porch = <22>;
59-
vsync-len = <13>;
60-
hsync-active = <0>;
61-
vsync-active = <0>;
62-
de-active = <1>;
63-
pixelclk-active = <1>;
64-
};
65-
6650
port {
6751
lcd_in: endpoint {
6852
remote-endpoint = <&dpi_out>;

‎arch/arm/boot/dts/dra7-evm-common.dtsi

Lines changed: 0 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -245,26 +245,6 @@
245245
rx-num-evt = <32>;
246246
};
247247

248-
&mailbox5 {
249-
status = "okay";
250-
mbox_ipu1_ipc3x: mbox_ipu1_ipc3x {
251-
status = "okay";
252-
};
253-
mbox_dsp1_ipc3x: mbox_dsp1_ipc3x {
254-
status = "okay";
255-
};
256-
};
257-
258-
&mailbox6 {
259-
status = "okay";
260-
mbox_ipu2_ipc3x: mbox_ipu2_ipc3x {
261-
status = "okay";
262-
};
263-
mbox_dsp2_ipc3x: mbox_dsp2_ipc3x {
264-
status = "okay";
265-
};
266-
};
267-
268248
&pcie1_rc {
269249
status = "okay";
270250
};

‎arch/arm/boot/dts/dra7-l4.dtsi

Lines changed: 16 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -1207,9 +1207,8 @@
12071207
<SYSC_IDLE_SMART>,
12081208
<SYSC_IDLE_SMART_WKUP>;
12091209
/* Domains (P, C): l4per_pwrdm, l4per_clkdm */
1210-
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>,
1211-
<&timer_sys_clk_div>;
1212-
clock-names = "fck", "timer_sys_ck";
1210+
clocks = <&l4per_clkctrl DRA7_L4PER_TIMER4_CLKCTRL 0>;
1211+
clock-names = "fck";
12131212
#address-cells = <1>;
12141213
#size-cells = <1>;
12151214
ranges = <0x0 0x36000 0x1000>;
@@ -3352,17 +3351,17 @@
33523351
<SYSC_IDLE_SMART>,
33533352
<SYSC_IDLE_SMART_WKUP>;
33543353
/* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3355-
clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>, <&timer_sys_clk_div>;
3356-
clock-names = "fck", "timer_sys_ck";
3354+
clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 0>;
3355+
clock-names = "fck";
33573356
#address-cells = <1>;
33583357
#size-cells = <1>;
33593358
ranges = <0x0 0x20000 0x1000>;
33603359

33613360
timer5: timer@0 {
33623361
compatible = "ti,omap5430-timer";
33633362
reg = <0x0 0x80>;
3364-
clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>;
3365-
clock-names = "fck";
3363+
clocks = <&ipu_clkctrl DRA7_IPU_TIMER5_CLKCTRL 24>, <&timer_sys_clk_div>;
3364+
clock-names = "fck", "timer_sys_ck";
33663365
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
33673366
};
33683367
};
@@ -3379,18 +3378,17 @@
33793378
<SYSC_IDLE_SMART>,
33803379
<SYSC_IDLE_SMART_WKUP>;
33813380
/* Domains (P, C): ipu_pwrdm, ipu_clkdm */
3382-
clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>,
3383-
<&timer_sys_clk_div>;
3384-
clock-names = "fck", "timer_sys_ck";
3381+
clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 0>;
3382+
clock-names = "fck";
33853383
#address-cells = <1>;
33863384
#size-cells = <1>;
33873385
ranges = <0x0 0x22000 0x1000>;
33883386

33893387
timer6: timer@0 {
33903388
compatible = "ti,omap5430-timer";
33913389
reg = <0x0 0x80>;
3392-
clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>;
3393-
clock-names = "fck";
3390+
clocks = <&ipu_clkctrl DRA7_IPU_TIMER6_CLKCTRL 24>, <&timer_sys_clk_div>;
3391+
clock-names = "fck", "timer_sys_ck";
33943392
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
33953393
};
33963394
};
@@ -3498,8 +3496,8 @@
34983496
timer14: timer@0 {
34993497
compatible = "ti,omap5430-timer";
35003498
reg = <0x0 0x80>;
3501-
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>;
3502-
clock-names = "fck";
3499+
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER14_CLKCTRL 24>, <&timer_sys_clk_div>;
3500+
clock-names = "fck", "timer_sys_ck";
35033501
interrupts = <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>;
35043502
ti,timer-pwm;
35053503
};
@@ -3526,8 +3524,8 @@
35263524
timer15: timer@0 {
35273525
compatible = "ti,omap5430-timer";
35283526
reg = <0x0 0x80>;
3529-
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>;
3530-
clock-names = "fck";
3527+
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER15_CLKCTRL 24>, <&timer_sys_clk_div>;
3528+
clock-names = "fck", "timer_sys_ck";
35313529
interrupts = <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>;
35323530
ti,timer-pwm;
35333531
};
@@ -3554,8 +3552,8 @@
35543552
timer16: timer@0 {
35553553
compatible = "ti,omap5430-timer";
35563554
reg = <0x0 0x80>;
3557-
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>;
3558-
clock-names = "fck";
3555+
clocks = <&l4per3_clkctrl DRA7_L4PER3_TIMER16_CLKCTRL 24>, <&timer_sys_clk_div>;
3556+
clock-names = "fck", "timer_sys_ck";
35593557
interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>;
35603558
ti,timer-pwm;
35613559
};

‎arch/arm/boot/dts/motorola-cpcap-mapphone.dtsi

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -13,8 +13,10 @@
1313
#interrupt-cells = <2>;
1414
#address-cells = <1>;
1515
#size-cells = <0>;
16-
spi-max-frequency = <3000000>;
16+
spi-max-frequency = <9600000>;
1717
spi-cs-high;
18+
spi-cpol;
19+
spi-cpha;
1820

1921
cpcap_adc: adc {
2022
compatible = "motorola,mapphone-cpcap-adc";

‎arch/arm/mach-omap2/omap_hwmod.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3489,7 +3489,7 @@ static const struct omap_hwmod_reset dra7_reset_quirks[] = {
34893489
};
34903490

34913491
static const struct omap_hwmod_reset omap_reset_quirks[] = {
3492-
{ .match = "dss", .len = 3, .reset = omap_dss_reset, },
3492+
{ .match = "dss_core", .len = 8, .reset = omap_dss_reset, },
34933493
{ .match = "hdq1w", .len = 5, .reset = omap_hdq1w_reset, },
34943494
{ .match = "i2c", .len = 3, .reset = omap_i2c_reset, },
34953495
{ .match = "wd_timer", .len = 8, .reset = omap2_wd_timer_reset, },

‎drivers/bus/ti-sysc.c

Lines changed: 74 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -221,6 +221,35 @@ static u32 sysc_read_sysstatus(struct sysc *ddata)
221221
return sysc_read(ddata, offset);
222222
}
223223

224+
/* Poll on reset status */
225+
static int sysc_wait_softreset(struct sysc *ddata)
226+
{
227+
u32 sysc_mask, syss_done, rstval;
228+
int syss_offset, error = 0;
229+
230+
syss_offset = ddata->offsets[SYSC_SYSSTATUS];
231+
sysc_mask = BIT(ddata->cap->regbits->srst_shift);
232+
233+
if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
234+
syss_done = 0;
235+
else
236+
syss_done = ddata->cfg.syss_mask;
237+
238+
if (syss_offset >= 0) {
239+
error = readx_poll_timeout(sysc_read_sysstatus, ddata, rstval,
240+
(rstval & ddata->cfg.syss_mask) ==
241+
syss_done,
242+
100, MAX_MODULE_SOFTRESET_WAIT);
243+
244+
} else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) {
245+
error = readx_poll_timeout(sysc_read_sysconfig, ddata, rstval,
246+
!(rstval & sysc_mask),
247+
100, MAX_MODULE_SOFTRESET_WAIT);
248+
}
249+
250+
return error;
251+
}
252+
224253
static int sysc_add_named_clock_from_child(struct sysc *ddata,
225254
const char *name,
226255
const char *optfck_name)
@@ -925,18 +954,47 @@ static int sysc_enable_module(struct device *dev)
925954
struct sysc *ddata;
926955
const struct sysc_regbits *regbits;
927956
u32 reg, idlemodes, best_mode;
957+
int error;
928958

929959
ddata = dev_get_drvdata(dev);
960+
961+
/*
962+
* Some modules like DSS reset automatically on idle. Enable optional
963+
* reset clocks and wait for OCP softreset to complete.
964+
*/
965+
if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET) {
966+
error = sysc_enable_opt_clocks(ddata);
967+
if (error) {
968+
dev_err(ddata->dev,
969+
"Optional clocks failed for enable: %i\n",
970+
error);
971+
return error;
972+
}
973+
}
974+
error = sysc_wait_softreset(ddata);
975+
if (error)
976+
dev_warn(ddata->dev, "OCP softreset timed out\n");
977+
if (ddata->cfg.quirks & SYSC_QUIRK_OPT_CLKS_IN_RESET)
978+
sysc_disable_opt_clocks(ddata);
979+
980+
/*
981+
* Some subsystem private interconnects, like DSS top level module,
982+
* need only the automatic OCP softreset handling with no sysconfig
983+
* register bits to configure.
984+
*/
930985
if (ddata->offsets[SYSC_SYSCONFIG] == -ENODEV)
931986
return 0;
932987

933988
regbits = ddata->cap->regbits;
934989
reg = sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
935990

936-
/* Set CLOCKACTIVITY, we only use it for ick */
991+
/*
992+
* Set CLOCKACTIVITY, we only use it for ick. And we only configure it
993+
* based on the SYSC_QUIRK_USE_CLOCKACT flag, not based on the hardware
994+
* capabilities. See the old HWMOD_SET_DEFAULT_CLOCKACT flag.
995+
*/
937996
if (regbits->clkact_shift >= 0 &&
938-
(ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT ||
939-
ddata->cfg.sysc_val & BIT(regbits->clkact_shift)))
997+
(ddata->cfg.quirks & SYSC_QUIRK_USE_CLOCKACT))
940998
reg |= SYSC_CLOCACT_ICK << regbits->clkact_shift;
941999

9421000
/* Set SIDLE mode */
@@ -991,6 +1049,9 @@ static int sysc_enable_module(struct device *dev)
9911049
sysc_write_sysconfig(ddata, reg);
9921050
}
9931051

1052+
/* Flush posted write */
1053+
sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1054+
9941055
if (ddata->module_enable_quirk)
9951056
ddata->module_enable_quirk(ddata);
9961057

@@ -1071,6 +1132,9 @@ static int sysc_disable_module(struct device *dev)
10711132
reg |= 1 << regbits->autoidle_shift;
10721133
sysc_write_sysconfig(ddata, reg);
10731134

1135+
/* Flush posted write */
1136+
sysc_read(ddata, ddata->offsets[SYSC_SYSCONFIG]);
1137+
10741138
return 0;
10751139
}
10761140

@@ -1488,7 +1552,7 @@ static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset,
14881552
bool lcd_en, digit_en, lcd2_en = false, lcd3_en = false;
14891553
const int lcd_en_mask = BIT(0), digit_en_mask = BIT(1);
14901554
int manager_count;
1491-
bool framedonetv_irq;
1555+
bool framedonetv_irq = true;
14921556
u32 val, irq_mask = 0;
14931557

14941558
switch (sysc_soc->soc) {
@@ -1505,6 +1569,7 @@ static u32 sysc_quirk_dispc(struct sysc *ddata, int dispc_offset,
15051569
break;
15061570
case SOC_AM4:
15071571
manager_count = 1;
1572+
framedonetv_irq = false;
15081573
break;
15091574
case SOC_UNKNOWN:
15101575
default:
@@ -1822,11 +1887,10 @@ static int sysc_legacy_init(struct sysc *ddata)
18221887
*/
18231888
static int sysc_reset(struct sysc *ddata)
18241889
{
1825-
int sysc_offset, syss_offset, sysc_val, rstval, error = 0;
1826-
u32 sysc_mask, syss_done;
1890+
int sysc_offset, sysc_val, error;
1891+
u32 sysc_mask;
18271892

18281893
sysc_offset = ddata->offsets[SYSC_SYSCONFIG];
1829-
syss_offset = ddata->offsets[SYSC_SYSSTATUS];
18301894

18311895
if (ddata->legacy_mode ||
18321896
ddata->cap->regbits->srst_shift < 0 ||
@@ -1835,11 +1899,6 @@ static int sysc_reset(struct sysc *ddata)
18351899

18361900
sysc_mask = BIT(ddata->cap->regbits->srst_shift);
18371901

1838-
if (ddata->cfg.quirks & SYSS_QUIRK_RESETDONE_INVERTED)
1839-
syss_done = 0;
1840-
else
1841-
syss_done = ddata->cfg.syss_mask;
1842-
18431902
if (ddata->pre_reset_quirk)
18441903
ddata->pre_reset_quirk(ddata);
18451904

@@ -1856,18 +1915,9 @@ static int sysc_reset(struct sysc *ddata)
18561915
if (ddata->post_reset_quirk)
18571916
ddata->post_reset_quirk(ddata);
18581917

1859-
/* Poll on reset status */
1860-
if (syss_offset >= 0) {
1861-
error = readx_poll_timeout(sysc_read_sysstatus, ddata, rstval,
1862-
(rstval & ddata->cfg.syss_mask) ==
1863-
syss_done,
1864-
100, MAX_MODULE_SOFTRESET_WAIT);
1865-
1866-
} else if (ddata->cfg.quirks & SYSC_QUIRK_RESET_STATUS) {
1867-
error = readx_poll_timeout(sysc_read_sysconfig, ddata, rstval,
1868-
!(rstval & sysc_mask),
1869-
100, MAX_MODULE_SOFTRESET_WAIT);
1870-
}
1918+
error = sysc_wait_softreset(ddata);
1919+
if (error)
1920+
dev_warn(ddata->dev, "OCP softreset timed out\n");
18711921

18721922
if (ddata->reset_done_quirk)
18731923
ddata->reset_done_quirk(ddata);

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