@@ -149,7 +149,7 @@ struct sh_msiof_spi_priv {
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#define SIFCTR_TFWM_8 5U /* Transfer Request when 8 empty stages */
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#define SIFCTR_TFWM_4 6U /* Transfer Request when 4 empty stages */
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#define SIFCTR_TFWM_1 7U /* Transfer Request when 1 empty stage */
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- #define SIFCTR_TFUA GENMASK(26 , 20) /* Transmit FIFO Usable Area */
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+ #define SIFCTR_TFUA GENMASK(28 , 20) /* Transmit FIFO Usable Area */
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#define SIFCTR_RFWM GENMASK(15, 13) /* Receive FIFO Watermark */
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#define SIFCTR_RFWM_1 0U /* Transfer Request when 1 valid stages */
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#define SIFCTR_RFWM_4 1U /* Transfer Request when 4 valid stages */
@@ -1113,6 +1113,15 @@ static const struct sh_msiof_chipdata rcar_gen3_data = {
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.min_div_pow = 1 ,
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};
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+ static const struct sh_msiof_chipdata rcar_gen4_data = {
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+ .bits_per_word_mask = SPI_BPW_MASK (8 ) | SPI_BPW_MASK (16 ) |
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+ SPI_BPW_MASK (24 ) | SPI_BPW_MASK (32 ),
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+ .tx_fifo_size = 256 ,
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+ .rx_fifo_size = 256 ,
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+ .ctlr_flags = SPI_CONTROLLER_MUST_TX ,
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+ .min_div_pow = 1 ,
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+ };
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+
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static const struct sh_msiof_chipdata rcar_r8a7795_data = {
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.bits_per_word_mask = SPI_BPW_MASK (8 ) | SPI_BPW_MASK (16 ) |
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SPI_BPW_MASK (24 ) | SPI_BPW_MASK (32 ),
@@ -1128,7 +1137,9 @@ static const struct of_device_id sh_msiof_match[] __maybe_unused = {
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{ .compatible = "renesas,rcar-gen2-msiof" , .data = & rcar_gen2_data },
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{ .compatible = "renesas,msiof-r8a7795" , .data = & rcar_r8a7795_data },
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{ .compatible = "renesas,rcar-gen3-msiof" , .data = & rcar_gen3_data },
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- { .compatible = "renesas,rcar-gen4-msiof" , .data = & rcar_gen3_data },
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+ { .compatible = "renesas,msiof-r8a779a0" , .data = & rcar_gen3_data },
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+ { .compatible = "renesas,msiof-r8a779f0" , .data = & rcar_gen3_data },
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+ { .compatible = "renesas,rcar-gen4-msiof" , .data = & rcar_gen4_data },
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{ .compatible = "renesas,sh-msiof" , .data = & sh_data }, /* Deprecated */
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{ /* sentinel */ }
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};
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