Skip to content

Commit 5b91dc7

Browse files
geertubroonie
authored andcommitted
spi: sh-msiof: Increase TX FIFO size for R-Car V4H/V4M
The MSIOF transmit FIFOs on R-Car V4H and V4M have 256 stages. Add a new family-specific match entry to handle this. Add quirk match entries for older R-Car Gen4 Socs (R-Car V3U and S4-8) that have transmit FIFOs with only 64 stages, just like on R-Car Gen3. Update the (unused) definition of SIFCTR_TFUA for consistency. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://patch.msgid.link/69cb5fc48f034d37484fa127b9864a1971a83417.1747401908.git.geert+renesas@glider.be Signed-off-by: Mark Brown <[email protected]>
1 parent f669c28 commit 5b91dc7

File tree

1 file changed

+13
-2
lines changed

1 file changed

+13
-2
lines changed

drivers/spi/spi-sh-msiof.c

Lines changed: 13 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -149,7 +149,7 @@ struct sh_msiof_spi_priv {
149149
#define SIFCTR_TFWM_8 5U /* Transfer Request when 8 empty stages */
150150
#define SIFCTR_TFWM_4 6U /* Transfer Request when 4 empty stages */
151151
#define SIFCTR_TFWM_1 7U /* Transfer Request when 1 empty stage */
152-
#define SIFCTR_TFUA GENMASK(26, 20) /* Transmit FIFO Usable Area */
152+
#define SIFCTR_TFUA GENMASK(28, 20) /* Transmit FIFO Usable Area */
153153
#define SIFCTR_RFWM GENMASK(15, 13) /* Receive FIFO Watermark */
154154
#define SIFCTR_RFWM_1 0U /* Transfer Request when 1 valid stages */
155155
#define SIFCTR_RFWM_4 1U /* Transfer Request when 4 valid stages */
@@ -1113,6 +1113,15 @@ static const struct sh_msiof_chipdata rcar_gen3_data = {
11131113
.min_div_pow = 1,
11141114
};
11151115

1116+
static const struct sh_msiof_chipdata rcar_gen4_data = {
1117+
.bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
1118+
SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
1119+
.tx_fifo_size = 256,
1120+
.rx_fifo_size = 256,
1121+
.ctlr_flags = SPI_CONTROLLER_MUST_TX,
1122+
.min_div_pow = 1,
1123+
};
1124+
11161125
static const struct sh_msiof_chipdata rcar_r8a7795_data = {
11171126
.bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) |
11181127
SPI_BPW_MASK(24) | SPI_BPW_MASK(32),
@@ -1128,7 +1137,9 @@ static const struct of_device_id sh_msiof_match[] __maybe_unused = {
11281137
{ .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data },
11291138
{ .compatible = "renesas,msiof-r8a7795", .data = &rcar_r8a7795_data },
11301139
{ .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data },
1131-
{ .compatible = "renesas,rcar-gen4-msiof", .data = &rcar_gen3_data },
1140+
{ .compatible = "renesas,msiof-r8a779a0", .data = &rcar_gen3_data },
1141+
{ .compatible = "renesas,msiof-r8a779f0", .data = &rcar_gen3_data },
1142+
{ .compatible = "renesas,rcar-gen4-msiof", .data = &rcar_gen4_data },
11321143
{ .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */
11331144
{ /* sentinel */ }
11341145
};

0 commit comments

Comments
 (0)