@@ -3041,6 +3041,16 @@ static int mmhub_err_codes[] = {
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CODE_VML2 , CODE_VML2_WALKER , CODE_MMCANE ,
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};
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+ static int vcn_err_codes [] = {
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+ CODE_VIDD , CODE_VIDV ,
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+ };
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+ static int jpeg_err_codes [] = {
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+ CODE_JPEG0S , CODE_JPEG0D , CODE_JPEG1S , CODE_JPEG1D ,
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+ CODE_JPEG2S , CODE_JPEG2D , CODE_JPEG3S , CODE_JPEG3D ,
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+ CODE_JPEG4S , CODE_JPEG4D , CODE_JPEG5S , CODE_JPEG5D ,
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+ CODE_JPEG6S , CODE_JPEG6D , CODE_JPEG7S , CODE_JPEG7D ,
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+ };
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+
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static const struct mca_ras_info mca_ras_table [] = {
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{
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.blkid = AMDGPU_RAS_BLOCK__UMC ,
@@ -3069,6 +3079,20 @@ static const struct mca_ras_info mca_ras_table[] = {
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.blkid = AMDGPU_RAS_BLOCK__XGMI_WAFL ,
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.ip = AMDGPU_MCA_IP_PCS_XGMI ,
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.get_err_count = mca_pcs_xgmi_mca_get_err_count ,
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+ }, {
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+ .blkid = AMDGPU_RAS_BLOCK__VCN ,
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+ .ip = AMDGPU_MCA_IP_SMU ,
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+ .err_code_array = vcn_err_codes ,
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+ .err_code_count = ARRAY_SIZE (vcn_err_codes ),
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+ .get_err_count = mca_smu_mca_get_err_count ,
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+ .bank_is_valid = mca_smu_bank_is_valid ,
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+ }, {
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+ .blkid = AMDGPU_RAS_BLOCK__JPEG ,
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+ .ip = AMDGPU_MCA_IP_SMU ,
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+ .err_code_array = jpeg_err_codes ,
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+ .err_code_count = ARRAY_SIZE (jpeg_err_codes ),
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+ .get_err_count = mca_smu_mca_get_err_count ,
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+ .bank_is_valid = mca_smu_bank_is_valid ,
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},
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};
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