drm/i915: Correctly set SFC capability for video engines

SFC capability of video engines is not set correctly because i915
is testing for incorrect bits.

Fixes: c5d3e39 ("drm/i915: Engine discovery query")
Cc: Matt Roper <[email protected]>
Cc: Tvrtko Ursulin <[email protected]>
Signed-off-by: Venkata Sandeep Dhanalakota <[email protected]>
Signed-off-by: Daniele Ceraolo Spurio <[email protected]>
Reviewed-by: Tvrtko Ursulin <[email protected]>
Cc: <[email protected]> # v5.3+
Signed-off-by: Chris Wilson <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
(cherry picked from commit ad18fa0)
Signed-off-by: Rodrigo Vivi <[email protected]>

Author: vsdhanal

drivers/gpu/drm/i915/gt/intel_engine_cs.c

@@ -371,7 +371,8 @@ static void __setup_engine_capabilities(struct intel_engine_cs *engine)
 		 * instances.
 		 */
 		if ((INTEL_GEN(i915) >= 11 &&
-		     engine->gt->info.vdbox_sfc_access & engine->mask) ||
+		     (engine->gt->info.vdbox_sfc_access &
+		      BIT(engine->instance))) ||
 		    (INTEL_GEN(i915) >= 9 && engine->instance == 0))
 			engine->uabi_capabilities |=
 				I915_VIDEO_AND_ENHANCE_CLASS_CAPABILITY_SFC;