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remoteproc: mediatek: Handle MT8195 SCP core 1 watchdog timeout
The MT8195 SCP core 1 watchdog timeout needs to be handled in the SCP core 0 IRQ handler because the MT8195 SCP core 1 watchdog timeout IRQ is wired on the same IRQ entry for core 0 watchdog timeout. MT8195 SCP has a watchdog status register to identify the watchdog timeout source when IRQ triggered. Signed-off-by: Tinghan Shen <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Tested-by: AngeloGioacchino Del Regno <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Mathieu Poirier <[email protected]>
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drivers/remoteproc/mtk_common.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -55,6 +55,10 @@
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#define MT8192_CORE0_WDT_IRQ 0x10030
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#define MT8192_CORE0_WDT_CFG 0x10034
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#define MT8195_SYS_STATUS 0x4004
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#define MT8195_CORE0_WDT BIT(16)
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#define MT8195_CORE1_WDT BIT(17)
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#define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4)
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#define MT8195_CPU1_SRAM_PD 0x1084
@@ -63,6 +67,7 @@
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#define MT8195_CORE1_SW_RSTN_CLR 0x20000
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#define MT8195_CORE1_SW_RSTN_SET 0x20004
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#define MT8195_CORE1_MEM_ATT_PREDEF 0x20008
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#define MT8195_CORE1_WDT_IRQ 0x20030
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#define MT8195_CORE1_WDT_CFG 0x20034
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#define MT8195_SEC_CTRL 0x85000

drivers/remoteproc/mtk_scp.c

Lines changed: 24 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -222,6 +222,29 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp)
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}
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}
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static void mt8195_scp_irq_handler(struct mtk_scp *scp)
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{
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u32 scp_to_host;
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scp_to_host = readl(scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_SET);
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if (scp_to_host & MT8192_SCP_IPC_INT_BIT) {
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scp_ipi_handler(scp);
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} else {
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u32 reason = readl(scp->cluster->reg_base + MT8195_SYS_STATUS);
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if (reason & MT8195_CORE0_WDT)
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writel(1, scp->cluster->reg_base + MT8192_CORE0_WDT_IRQ);
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if (reason & MT8195_CORE1_WDT)
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writel(1, scp->cluster->reg_base + MT8195_CORE1_WDT_IRQ);
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scp_wdt_handler(scp, reason);
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}
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writel(scp_to_host, scp->cluster->reg_base + MT8192_SCP2APMCU_IPC_CLR);
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}
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static void mt8195_scp_c1_irq_handler(struct mtk_scp *scp)
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{
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u32 scp_to_host;
@@ -1256,7 +1279,7 @@ static const struct mtk_scp_of_data mt8192_of_data = {
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static const struct mtk_scp_of_data mt8195_of_data = {
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.scp_clk_get = mt8195_scp_clk_get,
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.scp_before_load = mt8195_scp_before_load,
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.scp_irq_handler = mt8192_scp_irq_handler,
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.scp_irq_handler = mt8195_scp_irq_handler,
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.scp_reset_assert = mt8192_scp_reset_assert,
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.scp_reset_deassert = mt8192_scp_reset_deassert,
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.scp_stop = mt8195_scp_stop,

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