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| 1 | +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) |
| 2 | +%YAML 1.2 |
| 3 | +--- |
| 4 | +$id: http://devicetree.org/schemas/clock/samsung,exynos850-clock.yaml# |
| 5 | +$schema: http://devicetree.org/meta-schemas/core.yaml# |
| 6 | + |
| 7 | +title: Samsung Exynos850 SoC clock controller |
| 8 | + |
| 9 | +maintainers: |
| 10 | + - Sam Protsenko <[email protected]> |
| 11 | + - Chanwoo Choi <[email protected]> |
| 12 | + - Krzysztof Kozlowski <[email protected]> |
| 13 | + - Sylwester Nawrocki <[email protected]> |
| 14 | + |
| 15 | + |
| 16 | +description: | |
| 17 | + Exynos850 clock controller is comprised of several CMU units, generating |
| 18 | + clocks for different domains. Those CMU units are modeled as separate device |
| 19 | + tree nodes, and might depend on each other. Root clocks in that clock tree are |
| 20 | + two external clocks:: OSCCLK (26 MHz) and RTCCLK (32768 Hz). Those external |
| 21 | + clocks must be defined as fixed-rate clocks in dts. |
| 22 | +
|
| 23 | + CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and |
| 24 | + dividers; all other leaf clocks (other CMUs) are usually derived from CMU_TOP. |
| 25 | +
|
| 26 | + Each clock is assigned an identifier and client nodes can use this identifier |
| 27 | + to specify the clock which they consume. All clocks available for usage |
| 28 | + in clock consumer nodes are defined as preprocessor macros in |
| 29 | + 'dt-bindings/clock/exynos850.h' header. |
| 30 | +
|
| 31 | +properties: |
| 32 | + compatible: |
| 33 | + enum: |
| 34 | + - samsung,exynos850-cmu-top |
| 35 | + - samsung,exynos850-cmu-core |
| 36 | + - samsung,exynos850-cmu-dpu |
| 37 | + - samsung,exynos850-cmu-hsi |
| 38 | + - samsung,exynos850-cmu-peri |
| 39 | + |
| 40 | + clocks: |
| 41 | + minItems: 1 |
| 42 | + maxItems: 5 |
| 43 | + |
| 44 | + clock-names: |
| 45 | + minItems: 1 |
| 46 | + maxItems: 5 |
| 47 | + |
| 48 | + "#clock-cells": |
| 49 | + const: 1 |
| 50 | + |
| 51 | + reg: |
| 52 | + maxItems: 1 |
| 53 | + |
| 54 | +allOf: |
| 55 | + - if: |
| 56 | + properties: |
| 57 | + compatible: |
| 58 | + contains: |
| 59 | + const: samsung,exynos850-cmu-top |
| 60 | + |
| 61 | + then: |
| 62 | + properties: |
| 63 | + clocks: |
| 64 | + items: |
| 65 | + - description: External reference clock (26 MHz) |
| 66 | + |
| 67 | + clock-names: |
| 68 | + items: |
| 69 | + - const: oscclk |
| 70 | + |
| 71 | + - if: |
| 72 | + properties: |
| 73 | + compatible: |
| 74 | + contains: |
| 75 | + const: samsung,exynos850-cmu-core |
| 76 | + |
| 77 | + then: |
| 78 | + properties: |
| 79 | + clocks: |
| 80 | + items: |
| 81 | + - description: External reference clock (26 MHz) |
| 82 | + - description: CMU_CORE bus clock (from CMU_TOP) |
| 83 | + - description: CCI clock (from CMU_TOP) |
| 84 | + - description: eMMC clock (from CMU_TOP) |
| 85 | + - description: SSS clock (from CMU_TOP) |
| 86 | + |
| 87 | + clock-names: |
| 88 | + items: |
| 89 | + - const: oscclk |
| 90 | + - const: dout_core_bus |
| 91 | + - const: dout_core_cci |
| 92 | + - const: dout_core_mmc_embd |
| 93 | + - const: dout_core_sss |
| 94 | + |
| 95 | + - if: |
| 96 | + properties: |
| 97 | + compatible: |
| 98 | + contains: |
| 99 | + const: samsung,exynos850-cmu-dpu |
| 100 | + |
| 101 | + then: |
| 102 | + properties: |
| 103 | + clocks: |
| 104 | + items: |
| 105 | + - description: External reference clock (26 MHz) |
| 106 | + - description: DPU clock (from CMU_TOP) |
| 107 | + |
| 108 | + clock-names: |
| 109 | + items: |
| 110 | + - const: oscclk |
| 111 | + - const: dout_dpu |
| 112 | + |
| 113 | + - if: |
| 114 | + properties: |
| 115 | + compatible: |
| 116 | + contains: |
| 117 | + const: samsung,exynos850-cmu-hsi |
| 118 | + |
| 119 | + then: |
| 120 | + properties: |
| 121 | + clocks: |
| 122 | + items: |
| 123 | + - description: External reference clock (26 MHz) |
| 124 | + - description: External RTC clock (32768 Hz) |
| 125 | + - description: CMU_HSI bus clock (from CMU_TOP) |
| 126 | + - description: SD card clock (from CMU_TOP) |
| 127 | + - description: "USB 2.0 DRD clock (from CMU_TOP)" |
| 128 | + |
| 129 | + clock-names: |
| 130 | + items: |
| 131 | + - const: oscclk |
| 132 | + - const: rtcclk |
| 133 | + - const: dout_hsi_bus |
| 134 | + - const: dout_hsi_mmc_card |
| 135 | + - const: dout_hsi_usb20drd |
| 136 | + |
| 137 | + - if: |
| 138 | + properties: |
| 139 | + compatible: |
| 140 | + contains: |
| 141 | + const: samsung,exynos850-cmu-peri |
| 142 | + |
| 143 | + then: |
| 144 | + properties: |
| 145 | + clocks: |
| 146 | + items: |
| 147 | + - description: External reference clock (26 MHz) |
| 148 | + - description: CMU_PERI bus clock (from CMU_TOP) |
| 149 | + - description: UART clock (from CMU_TOP) |
| 150 | + - description: Parent clock for HSI2C and SPI (from CMU_TOP) |
| 151 | + |
| 152 | + clock-names: |
| 153 | + items: |
| 154 | + - const: oscclk |
| 155 | + - const: dout_peri_bus |
| 156 | + - const: dout_peri_uart |
| 157 | + - const: dout_peri_ip |
| 158 | + |
| 159 | +required: |
| 160 | + - compatible |
| 161 | + - "#clock-cells" |
| 162 | + - clocks |
| 163 | + - clock-names |
| 164 | + - reg |
| 165 | + |
| 166 | +additionalProperties: false |
| 167 | + |
| 168 | +examples: |
| 169 | + # Clock controller node for CMU_PERI |
| 170 | + - | |
| 171 | + #include <dt-bindings/clock/exynos850.h> |
| 172 | +
|
| 173 | + cmu_peri: clock-controller@10030000 { |
| 174 | + compatible = "samsung,exynos850-cmu-peri"; |
| 175 | + reg = <0x10030000 0x8000>; |
| 176 | + #clock-cells = <1>; |
| 177 | +
|
| 178 | + clocks = <&oscclk>, <&cmu_top CLK_DOUT_PERI_BUS>, |
| 179 | + <&cmu_top CLK_DOUT_PERI_UART>, |
| 180 | + <&cmu_top CLK_DOUT_PERI_IP>; |
| 181 | + clock-names = "oscclk", "dout_peri_bus", |
| 182 | + "dout_peri_uart", "dout_peri_ip"; |
| 183 | + }; |
| 184 | +
|
| 185 | +... |
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