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Merge tag 'drm-fixes-2019-11-22' of git://anongit.freedesktop.org/drm/drm
Pull drm fixes from Dave Airlie: "Two sets of fixes in here, one for amdgpu, and one for i915. The amdgpu ones are pretty small, i915's CI system seems to have a few problems in the last week or so, there is one major regression fix for fb_mmap, but there are a bunch of other issues fixed in there as well, oops, screen flashes and rcu related. amdgpu: - Remove experimental flag for navi14 - Fix confusing power message failures on older VI parts - Hang fix for gfxoff when using the read register interface - Two stability regression fixes for Raven i915: - Fix kernel oops on dumb_create ioctl on no crtc situation - Fix bad ugly colored flash on VLV/CHV related to gamma LUT update - Fix unity of the frequencies reported on PMU - Fix kernel oops on set_page_dirty using better locks around it - Protect the request pointer with RCU to prevent it being freed while we might need still - Make pool objects read-only - Restore physical addresses for fb_map to avoid corrupted page table" * tag 'drm-fixes-2019-11-22' of git://anongit.freedesktop.org/drm/drm: drm/i915/fbdev: Restore physical addresses for fb_mmap() Revert "drm/amd/display: enable S/G for RAVEN chip" drm/amdgpu: disable gfxoff on original raven drm/amdgpu: disable gfxoff when using register read interface drm/amd/powerplay: correct fine grained dpm force level setting drm/amd/powerplay: issue no PPSMC_MSG_GetCurrPkgPwr on unsupported ASICs drm/amdgpu: remove experimental flag for Navi14 drm/i915: make pool objects read-only drm/i915: Protect request peeking with RCU drm/i915/userptr: Try to acquire the page lock around set_page_dirty() drm/i915/pmu: "Frequency" is reported as accumulated cycles drm/i915: Preload LUTs if the hw isn't currently using them drm/i915: Don't oops in dumb_create ioctl if we have no crtcs
2 parents 81429eb + 51658c0 commit 5d867ab

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16 files changed

+183
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lines changed

‎drivers/gpu/drm/amd/amdgpu/amdgpu_display.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -511,7 +511,7 @@ uint32_t amdgpu_display_supported_domains(struct amdgpu_device *adev,
511511
* Also, don't allow GTT domain if the BO doens't have USWC falg set.
512512
*/
513513
if (adev->asic_type >= CHIP_CARRIZO &&
514-
adev->asic_type <= CHIP_RAVEN &&
514+
adev->asic_type < CHIP_RAVEN &&
515515
(adev->flags & AMD_IS_APU) &&
516516
(bo_flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC) &&
517517
amdgpu_bo_support_uswc(bo_flags) &&

‎drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1013,10 +1013,10 @@ static const struct pci_device_id pciidlist[] = {
10131013
{0x1002, 0x731B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
10141014
{0x1002, 0x731F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI10},
10151015
/* Navi14 */
1016-
{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
1017-
{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
1018-
{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
1019-
{0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14|AMD_EXP_HW_SUPPORT},
1016+
{0x1002, 0x7340, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1017+
{0x1002, 0x7341, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1018+
{0x1002, 0x7347, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
1019+
{0x1002, 0x734F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_NAVI14},
10201020

10211021
/* Renoir */
10221022
{0x1002, 0x1636, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RENOIR|AMD_IS_APU|AMD_EXP_HW_SUPPORT},

‎drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -649,15 +649,19 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
649649
return -ENOMEM;
650650
alloc_size = info->read_mmr_reg.count * sizeof(*regs);
651651

652-
for (i = 0; i < info->read_mmr_reg.count; i++)
652+
amdgpu_gfx_off_ctrl(adev, false);
653+
for (i = 0; i < info->read_mmr_reg.count; i++) {
653654
if (amdgpu_asic_read_register(adev, se_num, sh_num,
654655
info->read_mmr_reg.dword_offset + i,
655656
&regs[i])) {
656657
DRM_DEBUG_KMS("unallowed offset %#x\n",
657658
info->read_mmr_reg.dword_offset + i);
658659
kfree(regs);
660+
amdgpu_gfx_off_ctrl(adev, true);
659661
return -EFAULT;
660662
}
663+
}
664+
amdgpu_gfx_off_ctrl(adev, true);
661665
n = copy_to_user(out, regs, min(size, alloc_size));
662666
kfree(regs);
663667
return n ? -EFAULT : 0;

‎drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1038,8 +1038,13 @@ static void gfx_v9_0_check_if_need_gfxoff(struct amdgpu_device *adev)
10381038
case CHIP_VEGA20:
10391039
break;
10401040
case CHIP_RAVEN:
1041-
if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
1042-
&&((adev->gfx.rlc_fw_version != 106 &&
1041+
/* Disable GFXOFF on original raven. There are combinations
1042+
* of sbios and platforms that are not stable.
1043+
*/
1044+
if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8))
1045+
adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
1046+
else if (!(adev->rev_id >= 0x8 || adev->pdev->device == 0x15d8)
1047+
&&((adev->gfx.rlc_fw_version != 106 &&
10431048
adev->gfx.rlc_fw_version < 531) ||
10441049
(adev->gfx.rlc_fw_version == 53815) ||
10451050
(adev->gfx.rlc_feature_version < 1) ||

‎drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -688,7 +688,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
688688
*/
689689
if (adev->flags & AMD_IS_APU &&
690690
adev->asic_type >= CHIP_CARRIZO &&
691-
adev->asic_type <= CHIP_RAVEN)
691+
adev->asic_type < CHIP_RAVEN)
692692
init_data.flags.gpu_vm_support = true;
693693

694694
if (amdgpu_dc_feature_mask & DC_FBC_MASK)

‎drivers/gpu/drm/amd/powerplay/hwmgr/smu7_hwmgr.c

Lines changed: 18 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -3478,18 +3478,31 @@ static int smu7_get_pp_table_entry(struct pp_hwmgr *hwmgr,
34783478

34793479
static int smu7_get_gpu_power(struct pp_hwmgr *hwmgr, u32 *query)
34803480
{
3481+
struct amdgpu_device *adev = hwmgr->adev;
34813482
int i;
34823483
u32 tmp = 0;
34833484

34843485
if (!query)
34853486
return -EINVAL;
34863487

3487-
smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0);
3488-
tmp = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3489-
*query = tmp;
3488+
/*
3489+
* PPSMC_MSG_GetCurrPkgPwr is not supported on:
3490+
* - Hawaii
3491+
* - Bonaire
3492+
* - Fiji
3493+
* - Tonga
3494+
*/
3495+
if ((adev->asic_type != CHIP_HAWAII) &&
3496+
(adev->asic_type != CHIP_BONAIRE) &&
3497+
(adev->asic_type != CHIP_FIJI) &&
3498+
(adev->asic_type != CHIP_TONGA)) {
3499+
smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_GetCurrPkgPwr, 0);
3500+
tmp = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0);
3501+
*query = tmp;
34903502

3491-
if (tmp != 0)
3492-
return 0;
3503+
if (tmp != 0)
3504+
return 0;
3505+
}
34933506

34943507
smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PmStatusLogStart);
34953508
cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC,

‎drivers/gpu/drm/amd/powerplay/navi10_ppt.c

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -759,6 +759,12 @@ static int navi10_force_clk_levels(struct smu_context *smu,
759759
case SMU_UCLK:
760760
case SMU_DCEFCLK:
761761
case SMU_FCLK:
762+
/* There is only 2 levels for fine grained DPM */
763+
if (navi10_is_support_fine_grained_dpm(smu, clk_type)) {
764+
soft_max_level = (soft_max_level >= 1 ? 1 : 0);
765+
soft_min_level = (soft_min_level >= 1 ? 1 : 0);
766+
}
767+
762768
ret = smu_get_dpm_freq_by_index(smu, clk_type, soft_min_level, &min_freq);
763769
if (ret)
764770
return size;

‎drivers/gpu/drm/i915/display/intel_atomic.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -201,6 +201,7 @@ intel_crtc_duplicate_state(struct drm_crtc *crtc)
201201
crtc_state->update_wm_post = false;
202202
crtc_state->fb_changed = false;
203203
crtc_state->fifo_changed = false;
204+
crtc_state->preload_luts = false;
204205
crtc_state->wm.need_postvbl_update = false;
205206
crtc_state->fb_bits = 0;
206207
crtc_state->update_planes = 0;

‎drivers/gpu/drm/i915/display/intel_color.c

Lines changed: 61 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -990,6 +990,55 @@ void intel_color_commit(const struct intel_crtc_state *crtc_state)
990990
dev_priv->display.color_commit(crtc_state);
991991
}
992992

993+
static bool intel_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
994+
{
995+
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
996+
struct intel_atomic_state *state =
997+
to_intel_atomic_state(new_crtc_state->base.state);
998+
const struct intel_crtc_state *old_crtc_state =
999+
intel_atomic_get_old_crtc_state(state, crtc);
1000+
1001+
return !old_crtc_state->base.gamma_lut &&
1002+
!old_crtc_state->base.degamma_lut;
1003+
}
1004+
1005+
static bool chv_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
1006+
{
1007+
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
1008+
struct intel_atomic_state *state =
1009+
to_intel_atomic_state(new_crtc_state->base.state);
1010+
const struct intel_crtc_state *old_crtc_state =
1011+
intel_atomic_get_old_crtc_state(state, crtc);
1012+
1013+
/*
1014+
* CGM_PIPE_MODE is itself single buffered. We'd have to
1015+
* somehow split it out from chv_load_luts() if we wanted
1016+
* the ability to preload the CGM LUTs/CSC without tearing.
1017+
*/
1018+
if (old_crtc_state->cgm_mode || new_crtc_state->cgm_mode)
1019+
return false;
1020+
1021+
return !old_crtc_state->base.gamma_lut;
1022+
}
1023+
1024+
static bool glk_can_preload_luts(const struct intel_crtc_state *new_crtc_state)
1025+
{
1026+
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
1027+
struct intel_atomic_state *state =
1028+
to_intel_atomic_state(new_crtc_state->base.state);
1029+
const struct intel_crtc_state *old_crtc_state =
1030+
intel_atomic_get_old_crtc_state(state, crtc);
1031+
1032+
/*
1033+
* The hardware degamma is active whenever the pipe
1034+
* CSC is active. Thus even if the old state has no
1035+
* software degamma we need to avoid clobbering the
1036+
* linear hardware degamma mid scanout.
1037+
*/
1038+
return !old_crtc_state->csc_enable &&
1039+
!old_crtc_state->base.gamma_lut;
1040+
}
1041+
9931042
int intel_color_check(struct intel_crtc_state *crtc_state)
9941043
{
9951044
struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev);
@@ -1133,6 +1182,8 @@ static int i9xx_color_check(struct intel_crtc_state *crtc_state)
11331182
if (ret)
11341183
return ret;
11351184

1185+
crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1186+
11361187
return 0;
11371188
}
11381189

@@ -1185,6 +1236,8 @@ static int chv_color_check(struct intel_crtc_state *crtc_state)
11851236
if (ret)
11861237
return ret;
11871238

1239+
crtc_state->preload_luts = chv_can_preload_luts(crtc_state);
1240+
11881241
return 0;
11891242
}
11901243

@@ -1224,6 +1277,8 @@ static int ilk_color_check(struct intel_crtc_state *crtc_state)
12241277
if (ret)
12251278
return ret;
12261279

1280+
crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1281+
12271282
return 0;
12281283
}
12291284

@@ -1281,6 +1336,8 @@ static int ivb_color_check(struct intel_crtc_state *crtc_state)
12811336
if (ret)
12821337
return ret;
12831338

1339+
crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1340+
12841341
return 0;
12851342
}
12861343

@@ -1319,6 +1376,8 @@ static int glk_color_check(struct intel_crtc_state *crtc_state)
13191376
if (ret)
13201377
return ret;
13211378

1379+
crtc_state->preload_luts = glk_can_preload_luts(crtc_state);
1380+
13221381
return 0;
13231382
}
13241383

@@ -1368,6 +1427,8 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
13681427

13691428
crtc_state->csc_mode = icl_csc_mode(crtc_state);
13701429

1430+
crtc_state->preload_luts = intel_can_preload_luts(crtc_state);
1431+
13711432
return 0;
13721433
}
13731434

‎drivers/gpu/drm/i915/display/intel_display.c

Lines changed: 9 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2504,6 +2504,9 @@ u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
25042504
* the highest stride limits of them all.
25052505
*/
25062506
crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
2507+
if (!crtc)
2508+
return 0;
2509+
25072510
plane = to_intel_plane(crtc->base.primary);
25082511

25092512
return plane->max_stride(plane, pixel_format, modifier,
@@ -13740,6 +13743,11 @@ static void intel_update_crtc(struct intel_crtc *crtc,
1374013743
/* vblanks work again, re-enable pipe CRC. */
1374113744
intel_crtc_enable_pipe_crc(crtc);
1374213745
} else {
13746+
if (new_crtc_state->preload_luts &&
13747+
(new_crtc_state->base.color_mgmt_changed ||
13748+
new_crtc_state->update_pipe))
13749+
intel_color_load_luts(new_crtc_state);
13750+
1374313751
intel_pre_plane_update(old_crtc_state, new_crtc_state);
1374413752

1374513753
if (new_crtc_state->update_pipe)
@@ -14034,6 +14042,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
1403414042
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
1403514043
if (new_crtc_state->base.active &&
1403614044
!needs_modeset(new_crtc_state) &&
14045+
!new_crtc_state->preload_luts &&
1403714046
(new_crtc_state->base.color_mgmt_changed ||
1403814047
new_crtc_state->update_pipe))
1403914048
intel_color_load_luts(new_crtc_state);

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